threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ATMEL_PDMIC_H_
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#define __ATMEL_PDMIC_H_
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#include <linux/bitops.h>
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#define PDMIC_CR 0x00000000
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#define PDMIC_CR_SWRST 0x1
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#define PDMIC_CR_SWRST_MASK BIT(0)
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#define PDMIC_CR_SWRST_SHIFT (0)
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#define PDMIC_CR_ENPDM_DIS 0x0
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#define PDMIC_CR_ENPDM_EN 0x1
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#define PDMIC_CR_ENPDM_MASK BIT(4)
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#define PDMIC_CR_ENPDM_SHIFT (4)
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#define PDMIC_MR 0x00000004
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#define PDMIC_MR_CLKS_PCK 0x0
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#define PDMIC_MR_CLKS_GCK 0x1
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#define PDMIC_MR_CLKS_MASK BIT(4)
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#define PDMIC_MR_CLKS_SHIFT (4)
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#define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8)
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#define PDMIC_MR_PRESCAL_SHIFT (8)
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#define PDMIC_CDR 0x00000014
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#define PDMIC_IER 0x00000018
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#define PDMIC_IER_OVRE BIT(25)
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#define PDMIC_IDR 0x0000001c
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#define PDMIC_IDR_OVRE BIT(25)
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#define PDMIC_IMR 0x00000020
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#define PDMIC_ISR 0x00000024
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#define PDMIC_ISR_OVRE BIT(25)
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#define PDMIC_DSPR0 0x00000058
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#define PDMIC_DSPR0_HPFBYP_DIS 0x1
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#define PDMIC_DSPR0_HPFBYP_EN 0x0
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#define PDMIC_DSPR0_HPFBYP_MASK BIT(1)
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#define PDMIC_DSPR0_HPFBYP_SHIFT (1)
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#define PDMIC_DSPR0_SINBYP_DIS 0x1
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#define PDMIC_DSPR0_SINBYP_EN 0x0
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#define PDMIC_DSPR0_SINBYP_MASK BIT(2)
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#define PDMIC_DSPR0_SINBYP_SHIFT (2)
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#define PDMIC_DSPR0_SIZE_16_BITS 0x0
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#define PDMIC_DSPR0_SIZE_32_BITS 0x1
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#define PDMIC_DSPR0_SIZE_MASK BIT(3)
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#define PDMIC_DSPR0_SIZE_SHIFT (3)
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#define PDMIC_DSPR0_OSR_128 0x0
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#define PDMIC_DSPR0_OSR_64 0x1
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#define PDMIC_DSPR0_OSR_MASK GENMASK(6, 4)
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#define PDMIC_DSPR0_OSR_SHIFT (4)
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#define PDMIC_DSPR0_SCALE_MASK GENMASK(11, 8)
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#define PDMIC_DSPR0_SCALE_SHIFT (8)
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#define PDMIC_DSPR0_SHIFT_MASK GENMASK(15, 12)
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#define PDMIC_DSPR0_SHIFT_SHIFT (12)
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#define PDMIC_DSPR1 0x0000005c
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#define PDMIC_DSPR1_DGAIN_MASK GENMASK(14, 0)
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#define PDMIC_DSPR1_DGAIN_SHIFT (0)
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#define PDMIC_DSPR1_OFFSET_MASK GENMASK(31, 16)
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#define PDMIC_DSPR1_OFFSET_SHIFT (16)
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#define PDMIC_WPMR 0x000000e4
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#define PDMIC_WPSR 0x000000e8
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#endif
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