threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
|
|
* Device Tree constants for the Texas Instruments DP83867 PHY
|
|
*
|
|
* Author: Dan Murphy <dmurphy@ti.com>
|
|
*
|
|
* Copyright: (C) 2015 Texas Instruments, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_TI_DP83867_H
|
|
#define _DT_BINDINGS_TI_DP83867_H
|
|
|
|
/* PHY CTRL bits */
|
|
#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
|
|
#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
|
|
#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
|
|
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
|
|
|
|
/* RGMIIDCTL internal delay for rx and tx */
|
|
#define DP83867_RGMIIDCTL_250_PS 0x0
|
|
#define DP83867_RGMIIDCTL_500_PS 0x1
|
|
#define DP83867_RGMIIDCTL_750_PS 0x2
|
|
#define DP83867_RGMIIDCTL_1_NS 0x3
|
|
#define DP83867_RGMIIDCTL_1_25_NS 0x4
|
|
#define DP83867_RGMIIDCTL_1_50_NS 0x5
|
|
#define DP83867_RGMIIDCTL_1_75_NS 0x6
|
|
#define DP83867_RGMIIDCTL_2_00_NS 0x7
|
|
#define DP83867_RGMIIDCTL_2_25_NS 0x8
|
|
#define DP83867_RGMIIDCTL_2_50_NS 0x9
|
|
#define DP83867_RGMIIDCTL_2_75_NS 0xa
|
|
#define DP83867_RGMIIDCTL_3_00_NS 0xb
|
|
#define DP83867_RGMIIDCTL_3_25_NS 0xc
|
|
#define DP83867_RGMIIDCTL_3_50_NS 0xd
|
|
#define DP83867_RGMIIDCTL_3_75_NS 0xe
|
|
#define DP83867_RGMIIDCTL_4_00_NS 0xf
|
|
|
|
#endif
|