threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
3.9 KiB
C
108 lines
3.9 KiB
C
/*
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* Copyright (C) 2021 MediaTek Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef _DT_BINDINGS_MT6366_IRQ_H
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#define _DT_BINDINGS_MT6366_IRQ_H
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#define SP_BUCK 0
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#define SP_LDO 1
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#define SP_PSC 2
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#define SP_SCK 3
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#define SP_BM 4
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#define SP_HK 5
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#define SP_AUD 6
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#define SP_MISC 7
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#define INT_VPROC11_OC 0
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#define INT_VPROC12_OC 1
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#define INT_VCORE_OC 2
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#define INT_VGPU_OC 3
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#define INT_VMODEM_OC 4
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#define INT_VDRAM1_OC 5
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#define INT_VS1_OC 6
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#define INT_VS2_OC 7
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#define INT_VPA_OC 8
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#define INT_VCORE_PREOC 9
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#define INT_VFE28_OC 16
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#define INT_VXO22_OC 17
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#define INT_VRF18_OC 18
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#define INT_VRF12_OC 19
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#define INT_VEFUSE_OC 20
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#define INT_VCN33_OC 21
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#define INT_VCN28_OC 22
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#define INT_VCN18_OC 23
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#define INT_VM18_OC 24
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#define INT_VMDDR_OC 25
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#define INT_VSRAM_CORE_OC 26
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#define INT_VA12_OC 29
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#define INT_VAUX18_OC 30
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#define INT_VAUD28_OC 31
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#define INT_VIO28_OC 32
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#define INT_VIO18_OC 33
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#define INT_VSRAM_PROC11_OC 34
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#define INT_VSRAM_PROC12_OC 35
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#define INT_VSRAM_OTHERS_OC 36
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#define INT_VSRAM_GPU_OC 37
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#define INT_VDRAM2_OC 38
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#define INT_VMC_OC 39
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#define INT_VMCH_OC 40
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#define INT_VEMC_OC 41
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#define INT_VSIM1_OC 42
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#define INT_VSIM2_OC 43
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#define INT_VIBR_OC 44
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#define INT_VUSB_OC 45
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#define INT_VBIF28_OC 46
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#define INT_PWRKEY 48
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#define INT_HOMEKEY 49
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#define INT_PWRKEY_R 50
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#define INT_HOMEKEY_R 51
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#define INT_NI_LBAT_INT 52
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#define INT_CHRDET 53
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#define INT_CHRDET_EDGE 54
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#define INT_VCDT_HV_DET 55
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#define INT_RTC 64
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#define INT_FG_BAT0_H 80
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#define INT_FG_BAT0_L 81
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#define INT_FG_CUR_H 82
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#define INT_FG_CUR_L 83
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#define INT_FG_ZCV 84
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#define INT_FG_BAT1_H 85
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#define INT_FG_BAT1_L 86
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#define INT_FG_N_CHARGE_L 87
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#define INT_FG_IAVG_H 88
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#define INT_FG_IAVG_L 89
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#define INT_FG_TIME_H 90
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#define INT_FG_DISCHARGE 91
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#define INT_FG_CHARGE 92
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#define INT_BATON_LV 96
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#define INT_BATON_HT 97
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#define INT_BATON_BAT_IN 98
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#define INT_BATON_BAT_OUT 99
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#define INT_BIF 100
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#define INT_BAT_H 112
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#define INT_BAT_L 113
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#define INT_BAT2_H 114
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#define INT_BAT2_L 115
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#define INT_BAT_TEMP_H 116
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#define INT_BAT_TEMP_L 117
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#define INT_AUXADC_IMP 118
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#define INT_NAG_C_DLTV 119
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#define INT_AUDIO 128
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#define INT_ACCDET 133
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#define INT_ACCDET_EINT0 134
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#define INT_ACCDET_EINT1 135
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#define INT_SPI_CMD_ALERT 144
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#endif /* _DT_BINDINGS_MT6366_IRQ_H */
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