threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __WDT_HW_H__
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#define __WDT_HW_H__
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#define MTK_WDT_BASE toprgu_base
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#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000)
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#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004)
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#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008)
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#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C)
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#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010)
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#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014)
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#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018)
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#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020)
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#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024)
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#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030)
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#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034)
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#define MTK_WDT_DRAMC_CTL (MTK_WDT_BASE+0x0040)
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/*WDT_MODE*/
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#define MTK_WDT_MODE_KEYMASK (0xff00)
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#define MTK_WDT_MODE_KEY (0x22000000)
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#define MTK_WDT_MODE_DUAL_MODE (0x0040)
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#define MTK_WDT_MODE_IN_DIS (0x0020) /* Reserved */
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#define MTK_WDT_MODE_AUTO_RESTART (0x0010) /* Reserved */
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#define MTK_WDT_MODE_IRQ (0x0008)
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#define MTK_WDT_MODE_EXTEN (0x0004)
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#define MTK_WDT_MODE_EXT_POL (0x0002)
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#define MTK_WDT_MODE_ENABLE (0x0001)
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/*WDT_LENGTH*/
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#define MTK_WDT_LENGTH_TIME_OUT (0xffe0)
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#define MTK_WDT_LENGTH_KEYMASK (0x001f)
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#define MTK_WDT_LENGTH_KEY (0x0008)
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/*WDT_RESTART*/
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#define MTK_WDT_RESTART_KEY (0x1971)
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/*WDT_STATUS*/
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#define MTK_WDT_STATUS_HWWDT_RST (0x80000000)
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#define MTK_WDT_STATUS_SWWDT_RST (0x40000000)
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#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000)
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#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000)
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#define MTK_WDT_STATUS_SPMWDT_RST (0x0002)
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#define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001)
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#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18)
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#define MTK_WDT_STATUS_SECURITY_RST (1<<28)
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/*WDT_INTERVAL*/
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#define MTK_WDT_INTERVAL_MASK (0x0fff)
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/*WDT_SWRST*/
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#define MTK_WDT_SWRST_KEY (0x1209)
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/*WDT_SWSYSRST*/
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#define MTK_WDT_SWSYS_RST_PWRAP_SPI_CTL_RST (0x0800)
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#define MTK_WDT_SWSYS_RST_APMIXED_RST (0x0400)
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#define MTK_WDT_SWSYS_RST_MD_LITE_RST (0x0200)
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#define MTK_WDT_SWSYS_RST_INFRA_AO_RST (0x0100)
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#define MTK_WDT_SWSYS_RST_MD_RST (0x0080)
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#define MTK_WDT_SWSYS_RST_DDRPHY_RST (0x0040)
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#define MTK_WDT_SWSYS_RST_IMG_RST (0x0020)
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#define MTK_WDT_SWSYS_RST_VDEC_RST (0x0010)
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#define MTK_WDT_SWSYS_RST_VENC_RST (0x0008)
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#define MTK_WDT_SWSYS_RST_MFG_RST (0x0004)
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#define MTK_WDT_SWSYS_RST_DISP_RST (0x0002)
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#define MTK_WDT_SWSYS_RST_INFRA_RST (0x0001)
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/* #define MTK_WDT_SWSYS_RST_KEY (0x1500) */
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#define MTK_WDT_SWSYS_RST_KEY (0x88000000)
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/*MTK_WDT_REQ_IRQ*/
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#define MTK_WDT_REQ_IRQ_KEY (0x44000000)
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#define MTK_WDT_REQ_IRQ_DEBUG_EN (0x80000)
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#define MTK_WDT_REQ_IRQ_SPM_THERMAL_EN (0x0001)
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#define MTK_WDT_REQ_IRQ_SPM_SCPSYS_EN (0x0002)
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#define MTK_WDT_REQ_IRQ_THERMAL_EN (1<<18)
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/*MTK_WDT_REQ_MODE*/
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#define MTK_WDT_REQ_MODE_KEY (0x33000000)
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#define MTK_WDT_REQ_MODE_DEBUG_EN (0x80000)
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#define MTK_WDT_REQ_MODE_SPM_THERMAL (0x0001)
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#define MTK_WDT_REQ_MODE_SPM_SCPSYS (0x0002)
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#define MTK_WDT_REQ_MODE_THERMAL (1<<18)
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#endif /*__WDT_HW_H__*/
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