threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
217 lines
5.8 KiB
C
217 lines
5.8 KiB
C
/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _STAR_H_
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#define _STAR_H_
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ip.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/mii.h>
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#include <linux/version.h>
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#include <linux/dma-mapping.h>
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#include <linux/syscalls.h>
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#include <linux/fcntl.h>
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#include <linux/regulator/consumer.h>
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#include "star_mac.h"
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#include "star_phy.h"
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/* use rmii mode */
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#define CONFIG_STAR_USE_RMII_MODE
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#define ETH_MAX_FRAME_SIZE 1536
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#define ETH_SKB_ALIGNMENT 16
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#define TX_DESC_NUM 128
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#define RX_DESC_NUM 128
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#define TX_DESC_TOTAL_SIZE (sizeof(tx_desc) * TX_DESC_NUM)
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#define RX_DESC_TOTAL_SIZE (sizeof(rx_desc) * RX_DESC_NUM)
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#define ETH_EXTRA_PKT_LEN 36
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#define ETH_ADDR_LEN 6
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#define STAR_NAPI_WEIGHT (RX_DESC_NUM << 1)
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/* Star Ethernet Configuration*/
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/* ====================================== */
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#define star_intr_disable(dev) \
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star_set_reg(star_int_mask((dev)->base), 0xffffffff)
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#define star_intr_enable(dev) \
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star_set_reg(star_int_mask((dev)->base), 0)
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#define star_intr_clear(dev, intrStatus) \
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star_set_reg(star_int_sta((dev)->base), intrStatus)
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#define star_intr_status(dev) \
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star_get_reg(star_int_sta((dev)->base))
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#define star_intr_rx_enable(dev) \
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star_clear_bit(star_int_mask((dev)->base), STAR_INT_STA_RXC)
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#define star_intr_rx_disable(dev) \
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star_set_bit(star_int_mask((dev)->base), STAR_INT_STA_RXC)
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#define star_intr_mask(dev) \
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star_get_reg(star_int_mask((dev)->base))
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#define RX_RESUME BIT(2)
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#define RX_STOP BIT(1)
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#define RX_START BIT(0)
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#define dma_tx_start_and_reset_tx_desc(dev) \
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star_set_bit(star_tx_dma_ctrl((dev)->base), TX_START)
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#define dma_rx_start_and_reset_rx_desc(dev) \
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star_set_bit(star_rx_dma_ctrl((dev)->base), RX_START)
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#define star_dma_tx_enable(dev) \
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star_set_bit(star_tx_dma_ctrl((dev)->base), TX_RESUME)
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#define star_dma_tx_disable(dev) \
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star_set_bit(star_tx_dma_ctrl((dev)->base), TX_STOP)
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#define star_dma_rx_enable(dev) \
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star_set_bit(star_rx_dma_ctrl((dev)->base), RX_RESUME)
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#define star_dma_rx_disable(dev) \
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star_set_bit(star_rx_dma_ctrl((dev)->base), RX_STOP)
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#define star_dma_tx_resume(dev) star_dma_tx_enable(dev)
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#define star_dma_rx_resume(dev) star_dma_rx_enable(dev)
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#define star_reset_hash_table(dev) \
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star_set_bit(star_test1((dev)->base), STAR_TEST1_RST_HASH_BIST)
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#define star_dma_rx_crc_err(ctrl_len) ((ctrl_len & RX_CRCERR) ? 1 : 0)
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#define star_dma_rx_over_size(ctrl_len) ((ctrl_len & RX_OSIZE) ? 1 : 0)
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#define star_dma_rx_length(ctrl_len) \
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((ctrl_len >> RX_LEN_OFFSET) & RX_LEN_MASK)
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#define star_dma_tx_length(ctrl_len) \
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((ctrl_len >> TX_LEN_OFFSET) & TX_LEN_MASK)
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#define star_arl_promisc_enable(dev) \
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star_set_bit(STAR_ARL_CFG((dev)->base), STAR_ARL_CFG_MISCMODE)
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enum wol_type {
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WOL_NONE = 0,
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MAC_WOL,
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PHY_WOL,
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};
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/**
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* @brief structure for Star private data
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* @wol: ethernet mac wol type status
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* @wol_flag: normal wol: set true to enable, set false to disable.
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*/
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struct star_private_s {
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struct regulator *phy_regulator;
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struct clk *core_clk, *reg_clk, *trans_clk;
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star_dev star_dev;
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struct net_device *dev;
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dma_addr_t desc_dma_addr;
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uintptr_t desc_vir_addr;
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u32 phy_addr;
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/* star lock */
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spinlock_t lock;
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struct tasklet_struct dsr;
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bool tsk_tx;
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struct napi_struct napi;
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struct mii_if_info mii;
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struct input_dev *idev;
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bool opened;
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bool support_wol;
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bool support_rmii;
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int eint_irq;
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int eint_pin;
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enum wol_type wol;
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bool wol_flag;
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} star_private;
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struct eth_phy_ops {
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u32 addr;
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/* value of phy reg3(identifier2) */
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u32 phy_id;
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void (*init)(star_dev *sdev);
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void (*wol_enable)(struct net_device *netdev);
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void (*wol_disable)(struct net_device *netdev);
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};
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/* star mac memory barrier */
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#define star_mb() mb()
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#define STAR_PR_ERR(fmt...) pr_err("star: " fmt)
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#define STAR_PR_INFO(fmt...) pr_info("star: " fmt)
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#define STAR_PR_DEBUG(fmt...) pr_debug("star: " fmt)
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static inline void star_set_reg(void __iomem *reg, u32 value)
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{
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STAR_PR_DEBUG("%s(%p)=%08x\n", __func__, reg, value);
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iowrite32(value, reg);
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}
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static inline u32 star_get_reg(void __iomem *reg)
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{
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u32 data = ioread32(reg);
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STAR_PR_DEBUG("%s(%p)=%08x\n", __func__, reg, data);
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return data;
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}
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static inline void star_set_bit(void __iomem *reg, u32 bit)
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{
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u32 data = ioread32(reg);
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data |= bit;
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STAR_PR_DEBUG("%s(%p,bit:%08x)=%08x\n", __func__, reg, bit, data);
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iowrite32(data, reg);
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star_mb();
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}
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static inline void star_clear_bit(void __iomem *reg, u32 bit)
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{
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u32 data = ioread32(reg);
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data &= ~bit;
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STAR_PR_DEBUG(
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"%s(%p,bit:%08x)=%08x\n", __func__, reg, bit, data);
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iowrite32(data, reg);
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star_mb();
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}
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static inline u32 star_get_bit_mask(void __iomem *reg, u32 mask, u32 offset)
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{
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u32 data = ioread32(reg);
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data = ((data >> offset) & mask);
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STAR_PR_DEBUG(
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"%s(%p,mask:%08x,offset:%08x)=%08x(data)\n",
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__func__, reg, mask, offset, data);
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return data;
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}
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static inline u32 star_is_set_bit(void __iomem *reg, u32 bit)
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{
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u32 data = ioread32(reg);
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data &= bit;
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STAR_PR_DEBUG(
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"%s(%p,bit:%08x)=%08x\n", __func__, reg, bit, data);
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return data ? 1 : 0;
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}
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int star_get_wol_flag(star_private *star_prv);
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void star_set_wol_flag(star_private *star_prv, bool flag);
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int star_get_dbg_level(void);
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void star_set_dbg_level(int dbg);
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u32 star_dma_rx_valid(u32 ctrl_len);
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#endif /* _STAR_H_ */
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