threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
323 lines
8.9 KiB
C
323 lines
8.9 KiB
C
/* Copyright (C) 2018 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _AUTOK_CUST_H_
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#define _AUTOK_CUST_H_
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#define AUTOK_VERSION (0x18110817)
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struct AUTOK_PLAT_PARA_TX {
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unsigned int chip_hw_ver;
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u8 msdc0_hs400_clktx;
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u8 msdc0_hs400_cmdtx;
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u8 msdc0_hs400_dat0tx;
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u8 msdc0_hs400_dat1tx;
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u8 msdc0_hs400_dat2tx;
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u8 msdc0_hs400_dat3tx;
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u8 msdc0_hs400_dat4tx;
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u8 msdc0_hs400_dat5tx;
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u8 msdc0_hs400_dat6tx;
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u8 msdc0_hs400_dat7tx;
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u8 msdc0_hs400_txskew;
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u8 msdc0_ddr_ckd;
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u8 msdc1_ddr_ckd;
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u8 msdc2_ddr_ckd;
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u8 msdc0_clktx;
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u8 msdc0_cmdtx;
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u8 msdc0_dat0tx;
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u8 msdc0_dat1tx;
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u8 msdc0_dat2tx;
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u8 msdc0_dat3tx;
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u8 msdc0_dat4tx;
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u8 msdc0_dat5tx;
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u8 msdc0_dat6tx;
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u8 msdc0_dat7tx;
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u8 msdc0_txskew;
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u8 msdc1_clktx;
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u8 msdc1_sdr104_clktx;
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u8 msdc2_clktx;
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u8 sdio30_plus_clktx;
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u8 sdio30_plus_cmdtx;
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u8 sdio30_plus_dat0tx;
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u8 sdio30_plus_dat1tx;
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u8 sdio30_plus_dat2tx;
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u8 sdio30_plus_dat3tx;
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u8 msdc0_duty_bypass;
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u8 msdc0_hl_duty_sel;
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u8 msdc1_duty_bypass;
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u8 msdc1_hl_duty_sel;
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u8 msdc2_duty_bypass;
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u8 msdc2_hl_duty_sel;
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};
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struct AUTOK_PLAT_PARA_RX {
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unsigned int chip_hw_ver;
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u8 ckgen_val;
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u8 latch_en_cmd_hs400;
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u8 latch_en_crc_hs400;
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u8 latch_en_cmd_hs200;
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u8 latch_en_crc_hs200;
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u8 latch_en_cmd_ddr208;
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u8 latch_en_crc_ddr208;
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u8 latch_en_cmd_sd_sdr104;
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u8 latch_en_crc_sd_sdr104;
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u8 latch_en_cmd_sdio_sdr104;
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u8 latch_en_crc_sdio_sdr104;
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u8 latch_en_cmd_hs;
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u8 latch_en_crc_hs;
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u8 cmd_ta_val;
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u8 crc_ta_val;
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u8 busy_ma_val;
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u8 new_water_hs400;
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u8 new_water_hs200;
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u8 new_water_ddr208;
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u8 new_water_sdr104;
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u8 new_water_hs;
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u8 new_stop_hs400;
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u8 new_stop_hs200;
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u8 new_stop_ddr208;
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u8 new_stop_sdr104;
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u8 new_stop_hs;
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u8 old_water_hs400;
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u8 old_water_hs200;
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u8 old_water_ddr208;
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u8 old_water_sdr104;
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u8 old_water_hs;
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u8 old_stop_hs400;
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u8 old_stop_hs200;
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u8 old_stop_ddr208;
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u8 old_stop_sdr104;
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u8 old_stop_hs;
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u8 read_dat_cnt_hs400;
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u8 read_dat_cnt_ddr208;
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u8 end_bit_chk_cnt_hs400;
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u8 end_bit_chk_cnt_ddr208;
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u8 latchck_switch_cnt_hs400;
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u8 latchck_switch_cnt_ddr208;
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u8 ds_dly3_hs400;
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u8 ds_dly3_ddr208;
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};
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struct AUTOK_PLAT_PARA_MISC {
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unsigned int chip_hw_ver;
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u8 latch_ck_emmc_times;
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u8 latch_ck_sdio_times;
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u8 latch_ck_sd_times;
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u8 emmc_data_tx_tune;
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u8 data_tx_separate_tune;
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};
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struct AUTOK_PLAT_TOP_CTRL {
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u8 msdc0_rx_enhance_top;
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u8 msdc1_rx_enhance_top;
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u8 msdc2_rx_enhance_top;
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};
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struct AUTOK_PLAT_FUNC {
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unsigned int chip_hw_ver;
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u8 new_path_hs400;
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u8 new_path_hs200;
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u8 new_path_ddr208;
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u8 new_path_sdr104;
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u8 new_path_hs;
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u8 multi_sync;
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u8 rx_enhance;
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u8 r1b_check;
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u8 ddr50_fix;
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u8 fifo_1k;
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u8 latch_enhance;
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u8 msdc0_bypass_duty_modify;
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u8 msdc1_bypass_duty_modify;
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u8 msdc2_bypass_duty_modify;
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};
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#define get_platform_para_tx(autok_para_tx) \
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do { \
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autok_para_tx.msdc0_hs400_clktx = 0; \
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autok_para_tx.msdc0_hs400_cmdtx = 0; \
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autok_para_tx.msdc0_hs400_dat0tx = 0; \
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autok_para_tx.msdc0_hs400_dat1tx = 0; \
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autok_para_tx.msdc0_hs400_dat2tx = 0; \
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autok_para_tx.msdc0_hs400_dat3tx = 0; \
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autok_para_tx.msdc0_hs400_dat4tx = 0; \
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autok_para_tx.msdc0_hs400_dat5tx = 0; \
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autok_para_tx.msdc0_hs400_dat6tx = 0; \
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autok_para_tx.msdc0_hs400_dat7tx = 0; \
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autok_para_tx.msdc0_hs400_txskew = 0; \
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autok_para_tx.msdc0_ddr_ckd = 1; \
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autok_para_tx.msdc1_ddr_ckd = 0; \
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autok_para_tx.msdc2_ddr_ckd = 1; \
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autok_para_tx.msdc0_clktx = 0; \
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autok_para_tx.msdc0_cmdtx = 0; \
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autok_para_tx.msdc0_dat0tx = 0; \
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autok_para_tx.msdc0_dat1tx = 0; \
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autok_para_tx.msdc0_dat2tx = 0; \
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autok_para_tx.msdc0_dat3tx = 0; \
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autok_para_tx.msdc0_dat4tx = 0; \
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autok_para_tx.msdc0_dat5tx = 0; \
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autok_para_tx.msdc0_dat6tx = 0; \
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autok_para_tx.msdc0_dat7tx = 0; \
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autok_para_tx.msdc0_txskew = 0; \
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autok_para_tx.msdc1_clktx = 0; \
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autok_para_tx.msdc1_sdr104_clktx = 0; \
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autok_para_tx.msdc2_clktx = 0; \
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autok_para_tx.sdio30_plus_clktx = 0; \
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autok_para_tx.sdio30_plus_cmdtx = 0; \
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autok_para_tx.sdio30_plus_dat0tx = 0; \
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autok_para_tx.sdio30_plus_dat1tx = 0; \
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autok_para_tx.sdio30_plus_dat2tx = 0; \
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autok_para_tx.sdio30_plus_dat3tx = 0; \
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autok_para_tx.msdc0_duty_bypass = 0; \
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autok_para_tx.msdc0_hl_duty_sel = 0; \
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autok_para_tx.msdc1_duty_bypass = 0; \
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autok_para_tx.msdc1_hl_duty_sel = 0; \
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autok_para_tx.msdc2_duty_bypass = 0; \
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autok_para_tx.msdc2_hl_duty_sel = 0; \
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} while (0)
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#define get_platform_para_rx(autok_para_rx) \
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do { \
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autok_para_rx.ckgen_val = 0; \
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autok_para_rx.latch_en_cmd_hs400 = 3; \
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autok_para_rx.latch_en_crc_hs400 = 3; \
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autok_para_rx.latch_en_cmd_hs200 = 2; \
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autok_para_rx.latch_en_crc_hs200 = 2; \
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autok_para_rx.latch_en_cmd_ddr208 = 4; \
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autok_para_rx.latch_en_crc_ddr208 = 4; \
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autok_para_rx.latch_en_cmd_sd_sdr104 = 1; \
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autok_para_rx.latch_en_crc_sd_sdr104 = 1; \
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autok_para_rx.latch_en_cmd_sdio_sdr104 = 2; \
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autok_para_rx.latch_en_crc_sdio_sdr104 = 2; \
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autok_para_rx.latch_en_cmd_hs = 1; \
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autok_para_rx.latch_en_crc_hs = 1; \
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autok_para_rx.cmd_ta_val = 0; \
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autok_para_rx.crc_ta_val = 0; \
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autok_para_rx.busy_ma_val = 1; \
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autok_para_rx.new_water_hs400 = 8; \
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autok_para_rx.new_stop_hs400 = 3; \
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autok_para_rx.new_water_hs200 = 0; \
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autok_para_rx.new_stop_hs200 = 6; \
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autok_para_rx.new_water_ddr208 = 8; \
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autok_para_rx.new_stop_ddr208 = 3; \
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autok_para_rx.new_water_sdr104 = 0; \
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autok_para_rx.new_stop_sdr104 = 6; \
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autok_para_rx.new_water_hs = 8; \
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autok_para_rx.new_stop_hs = 3; \
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autok_para_rx.old_water_hs400 = 8; \
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autok_para_rx.old_stop_hs400 = 3; \
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autok_para_rx.old_water_hs200 = 0; \
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autok_para_rx.old_stop_hs200 = 6; \
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autok_para_rx.old_water_ddr208 = 8; \
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autok_para_rx.old_stop_ddr208 = 3; \
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autok_para_rx.old_water_sdr104 = 0; \
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autok_para_rx.old_stop_sdr104 = 6; \
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autok_para_rx.old_water_hs = 8; \
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autok_para_rx.old_stop_hs = 3; \
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autok_para_rx.read_dat_cnt_hs400 = 7; \
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autok_para_rx.read_dat_cnt_ddr208 = 0; \
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autok_para_rx.end_bit_chk_cnt_hs400 = 14; \
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autok_para_rx.end_bit_chk_cnt_ddr208 = 0; \
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autok_para_rx.latchck_switch_cnt_hs400 = 6; \
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autok_para_rx.latchck_switch_cnt_ddr208 = 0; \
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autok_para_rx.ds_dly3_hs400 = 20; \
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autok_para_rx.ds_dly3_ddr208 = 0; \
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} while (0)
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#define get_platform_para_misc(autok_para_misc) \
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do { \
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autok_para_misc.latch_ck_emmc_times = 10; \
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autok_para_misc.latch_ck_sdio_times = 20; \
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autok_para_misc.latch_ck_sd_times = 20; \
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autok_para_misc.emmc_data_tx_tune = 1; \
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autok_para_misc.data_tx_separate_tune = 0; \
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} while (0)
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#define get_platform_top_ctrl(autok_top_ctrl) \
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do { \
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autok_top_ctrl.msdc0_rx_enhance_top = 1; \
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autok_top_ctrl.msdc1_rx_enhance_top = 1; \
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autok_top_ctrl.msdc2_rx_enhance_top = 0; \
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} while (0)
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/*
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* emmc_data_tx_tune:0 use cmd24;1 use cmd23+cmd25;2:use cmdq cmd
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*/
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#define get_platform_func(autok_para_func) \
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do { \
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autok_para_func.new_path_hs400 = 1; \
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autok_para_func.new_path_hs200 = 1; \
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autok_para_func.new_path_ddr208 = 1; \
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autok_para_func.new_path_sdr104 = 1; \
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autok_para_func.new_path_hs = 1; \
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autok_para_func.multi_sync = 1; \
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autok_para_func.rx_enhance = 1; \
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autok_para_func.r1b_check = 1; \
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autok_para_func.ddr50_fix = 1; \
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autok_para_func.fifo_1k = 1; \
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autok_para_func.latch_enhance = 1; \
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autok_para_func.msdc0_bypass_duty_modify = 1; \
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autok_para_func.msdc1_bypass_duty_modify = 1; \
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autok_para_func.msdc2_bypass_duty_modify = 0; \
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} while (0)
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#define PORT0_PB0_RD_DAT_SEL_VALID
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#define PORT1_PB0_RD_DAT_SEL_VALID
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#define PORT3_PB0_RD_DAT_SEL_VALID
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#define MMC_QUE_TASK_PARAMS_RD 441
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#define MMC_QUE_TASK_PARAMS_WR 440
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#define MMC_SWITCH_CQ_EN 601
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#define MMC_SWITCH_CQ_DIS 600
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/*
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* reg define
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*/
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#define AUTOK_SDC_RX_ENH_EN (0x1 << 20) /* RW */
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#define AUTOK_TOP_SDC_RX_ENHANCE_EN (0x1 << 15) /* RW */
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/**********************************************************
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* Feature Control Defination *
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**********************************************************/
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#define AUTOK_EMMC_OFFLINE_TUNE_TX_ENABLE 0
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#define AUTOK_SD_CARD_OFFLINE_TUNE_TX_ENABLE 0
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#define AUTOK_SDIO_OFFLINE_TUNE_TX_ENABLE 1
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#define AUTOK_OFFLINE_CMD_H_TX_ENABLE 0
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#define AUTOK_OFFLINE_DAT_H_TX_ENABLE 1
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#define AUTOK_OFFLINE_CMD_D_RX_ENABLE 0
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#define AUTOK_OFFLINE_DAT_D_RX_ENABLE 1
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#define AUTOK_OFFLINE_TUNE_DEVICE_RX_ENABLE 1
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#define AUTOK_PARAM_DUMP_ENABLE 0
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#define SINGLE_EDGE_ONLINE_TUNE 0
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#define SDIO_PLUS_CMD_TUNE 1
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#define STOP_CLK_NEW_PATH 0
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#define DS_DLY3_SCAN 0
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#define CHIP_DENALI_3_DAT_TUNE 0
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#endif /* _AUTOK_CUST_H_ */
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