threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
146 lines
3.7 KiB
C
146 lines
3.7 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifdef pr_fmt
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#undef pr_fmt
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#endif
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#define pr_fmt(fmt) "["KBUILD_MODNAME"]" fmt
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#include <linux/io.h>
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#include "mtk_sd.h"
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#define FPGA_PWR_GPIO (0x10001E84)
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#define FPGA_PWR_GPIO_EO (0x10001E88)
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static void __iomem *fpga_pwr_gpio;
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static void __iomem *fpga_pwr_gpio_eo;
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#define PWR_GPIO (fpga_pwr_gpio)
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#define PWR_GPIO_EO (fpga_pwr_gpio_eo)
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#define PWR_MASK_VOL_33 (1 << 10)
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#define PWR_MASK_VOL_18 (1 << 9)
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#define PWR_MASK_CARD (1 << 8)
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#define PWR_MASK_VOL_33_MASK (~(1 << 10))
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#define PWR_MASK_CARD_MASK (~(1 << 8))
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#define PWR_MASK_VOL_18_MASK (~(1 << 9))
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void msdc_set_pwr_gpio_dir(void __iomem *fpga_pwr_gpio,
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void __iomem *fpga_pwr_gpio_eo)
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{
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u16 l_val;
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l_val = MSDC_READ16(PWR_GPIO_EO);
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MSDC_WRITE16(PWR_GPIO_EO,
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(l_val | /* PWR_GPIO_L4_DIR | */
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PWR_MASK_CARD | PWR_MASK_VOL_33 | PWR_MASK_VOL_18));
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l_val = MSDC_READ16(PWR_GPIO_EO);
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pr_debug("[%s]: pwr gpio dir = 0x%x\n", __func__, l_val);
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}
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void msdc_fpga_pwr_init(void)
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{
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if (fpga_pwr_gpio == NULL) {
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fpga_pwr_gpio = ioremap(FPGA_PWR_GPIO, 8);
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if (fpga_pwr_gpio == NULL) {
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pr_notice("[%s] msdc ioremap error\n", __func__);
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WARN_ON(1);
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}
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fpga_pwr_gpio_eo = fpga_pwr_gpio + 0x4;
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pr_notice("FPGA PWR_GPIO, PWR_GPIO_EO address 0x%p, 0x%p\n",
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fpga_pwr_gpio, fpga_pwr_gpio_eo);
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}
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msdc_set_pwr_gpio_dir(fpga_pwr_gpio, fpga_pwr_gpio_eo);
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}
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bool hwPowerOn_fpga(void)
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{
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u16 l_val;
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l_val = MSDC_READ16(PWR_GPIO);
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#ifdef CONFIG_MTK_EMMC_SUPPORT
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MSDC_WRITE16(PWR_GPIO, (l_val | PWR_MASK_VOL_18 | PWR_MASK_CARD));
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/* | PWR_GPIO_L4_DIR)); */
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#else
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MSDC_WRITE16(PWR_GPIO, (l_val | PWR_MASK_VOL_33 | PWR_MASK_CARD));
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/* | PWR_GPIO_L4_DIR)); */
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#endif
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l_val = MSDC_READ16(PWR_GPIO);
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pr_debug("[%s]: pwr gpio = 0x%x\n", __func__, l_val);
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return true;
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}
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EXPORT_SYMBOL(hwPowerOn_fpga);
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bool hwPowerSwitch_fpga(void)
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{
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u16 l_val;
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l_val = MSDC_READ16(PWR_GPIO);
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MSDC_WRITE16(PWR_GPIO, (l_val & ~(PWR_MASK_VOL_33)));
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l_val = MSDC_READ16(PWR_GPIO);
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MSDC_WRITE16(PWR_GPIO, (l_val | PWR_MASK_VOL_18));
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l_val = MSDC_READ16(PWR_GPIO);
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pr_debug("[%s]: pwr gpio = 0x%x\n", __func__, l_val);
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return true;
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}
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EXPORT_SYMBOL(hwPowerSwitch_fpga);
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bool hwPowerDown_fpga(void)
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{
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u16 l_val;
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l_val = MSDC_READ16(PWR_GPIO);
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#ifdef CONFIG_MTK_EMMC_SUPPORT
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MSDC_WRITE16(PWR_GPIO,
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(l_val & ~(PWR_MASK_VOL_18 | PWR_MASK_CARD)));
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#else
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MSDC_WRITE16(PWR_GPIO,
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(l_val & ~(PWR_MASK_VOL_18 | PWR_MASK_VOL_33 | PWR_MASK_CARD)));
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#endif
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l_val = MSDC_READ16(PWR_GPIO);
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pr_debug("[%s]: pwr gpio = 0x%x\n", __func__, l_val);
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return true;
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}
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EXPORT_SYMBOL(hwPowerDown_fpga);
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void msdc_fpga_power(struct msdc_host *host, u32 on)
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{
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if (on)
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hwPowerOn_fpga();
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else
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hwPowerDown_fpga();
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}
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void msdc_sd_power_switch(struct msdc_host *host, u32 on)
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{
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if (on)
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hwPowerSwitch_fpga();
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}
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void msdc_select_clksrc(struct msdc_host *host, int clksrc)
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{
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host->hclk = msdc_get_hclk(host->id, clksrc);
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host->hw->clk_src = clksrc;
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pr_notice("[%s]: msdc%d select clk_src as %d(%dKHz)\n", __func__,
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host->id, clksrc, host->hclk/1000);
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}
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/* do we need sync object or not */
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void msdc_clk_status(int *status)
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{
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}
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