threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
104 lines
4.2 KiB
C
104 lines
4.2 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __VCODEC_DRIVER_H__
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#define __VCODEC_DRIVER_H__
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#include <linux/regulator/consumer.h>
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#define MFV_IOC_MAGIC 'M'
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/* below is control message */
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#define MFV_TEST_CMD _IO(MFV_IOC_MAGIC, 0x00)
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#define MFV_INIT_CMD _IO(MFV_IOC_MAGIC, 0x01)
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#define MFV_DEINIT_CMD _IO(MFV_IOC_MAGIC, 0x02)
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/* P_MFV_DRV_CMD_QUEUE_T */
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#define MFV_SET_CMD_CMD _IOW(MFV_IOC_MAGIC, 0x03, unsigned int)
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/* HAL_POWER_T * */
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#define MFV_SET_PWR_CMD _IOW(MFV_IOC_MAGIC, 0x04, unsigned int)
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/* HAL_ISR_T * */
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#define MFV_SET_ISR_CMD _IOW(MFV_IOC_MAGIC, 0x05, unsigned int)
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#define MFV_ALLOC_MEM_CMD _IOW(MFV_IOC_MAGIC, 0x06, unsigned int)
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#define MFV_FREE_MEM_CMD _IOW(MFV_IOC_MAGIC, 0x07, unsigned int)
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/* unsigned int* */
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#define MFV_MAKE_PMEM_TO_NONCACHED _IOW(MFV_IOC_MAGIC, 0x08, unsigned int)
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/* VAL_INTMEM_T* */
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#define MFV_ALLOC_INT_MEM_CMD _IOW(MFV_IOC_MAGIC, 0x09, unsigned int)
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/* VAL_INTMEM_T* */
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#define MFV_FREE_INT_MEM_CMD _IOW(MFV_IOC_MAGIC, 0x0a, unsigned int)
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/* HAL_POWER_T * */
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#define VCODEC_WAITISR _IOW(MFV_IOC_MAGIC, 0x0b, unsigned int)
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/* VAL_HW_LOCK_T * */
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#define VCODEC_LOCKHW _IOW(MFV_IOC_MAGIC, 0x0d, unsigned int)
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/* HAL_POWER_T * */
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#define VCODEC_PMEM_FLUSH _IOW(MFV_IOC_MAGIC, 0x10, unsigned int)
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/* HAL_POWER_T * */
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#define VCODEC_PMEM_CLEAN _IOW(MFV_IOC_MAGIC, 0x11, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_INC_SYSRAM_USER _IOW(MFV_IOC_MAGIC, 0x13, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_DEC_SYSRAM_USER _IOW(MFV_IOC_MAGIC, 0x14, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_INC_ENC_EMI_USER _IOW(MFV_IOC_MAGIC, 0x15, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_DEC_ENC_EMI_USER _IOW(MFV_IOC_MAGIC, 0x16, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_INC_DEC_EMI_USER _IOW(MFV_IOC_MAGIC, 0x17, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_DEC_DEC_EMI_USER _IOW(MFV_IOC_MAGIC, 0x18, unsigned int)
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/* VAL_VCODEC_OAL_HW_REGISTER_T * */
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#define VCODEC_INITHWLOCK _IOW(MFV_IOC_MAGIC, 0x20, unsigned int)
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/* VAL_VCODEC_OAL_HW_REGISTER_T * */
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#define VCODEC_DEINITHWLOCK _IOW(MFV_IOC_MAGIC, 0x21, unsigned int)
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/* VAL_MEMORY_T * */
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#define VCODEC_ALLOC_NON_CACHE_BUFFER _IOW(MFV_IOC_MAGIC, 0x22, unsigned int)
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/* VAL_MEMORY_T * */
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#define VCODEC_FREE_NON_CACHE_BUFFER _IOW(MFV_IOC_MAGIC, 0x23, unsigned int)
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/* VAL_VCODEC_THREAD_ID_T * */
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#define VCODEC_SET_THREAD_ID _IOW(MFV_IOC_MAGIC, 0x24, unsigned int)
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/* VAL_INTMEM_T * */
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#define VCODEC_SET_SYSRAM_INFO _IOW(MFV_IOC_MAGIC, 0x25, unsigned int)
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/* VAL_INTMEM_T * */
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#define VCODEC_GET_SYSRAM_INFO _IOW(MFV_IOC_MAGIC, 0x26, unsigned int)
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/* HAL_POWER_T * */
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#define VCODEC_INC_PWR_USER _IOW(MFV_IOC_MAGIC, 0x27, unsigned int)
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/* HAL_POWER_T * */
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#define VCODEC_DEC_PWR_USER _IOW(MFV_IOC_MAGIC, 0x28, unsigned int)
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/* VAL_VCODEC_CPU_LOADING_INFO_T * */
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#define VCODEC_GET_CPU_LOADING_INFO _IOW(MFV_IOC_MAGIC, 0x29, unsigned int)
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/* VAL_VCODEC_CORE_LOADING_T * */
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#define VCODEC_GET_CORE_LOADING _IOW(MFV_IOC_MAGIC, 0x30, unsigned int)
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/* int * */
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#define VCODEC_GET_CORE_NUMBER _IOW(MFV_IOC_MAGIC, 0x31, unsigned int)
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/* VAL_VCODEC_CPU_OPP_LIMIT_T * */
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#define VCODEC_SET_CPU_OPP_LIMIT _IOW(MFV_IOC_MAGIC, 0x32, unsigned int)
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/* VAL_HW_LOCK_T * */
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#define VCODEC_UNLOCKHW _IOW(MFV_IOC_MAGIC, 0x33, unsigned int)
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/* VAL_UINT32_T * */
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#define VCODEC_MB _IOW(MFV_IOC_MAGIC, 0x34, unsigned int)
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/* VAL_BOOL_T * */
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#define VCODEC_SET_LOG_COUNT _IOW(MFV_IOC_MAGIC, 0x35, unsigned int)
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/* VAL_BOOL_T * */
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#define VCODEC_SET_AV_TASK_GROUP _IOW(MFV_IOC_MAGIC, 0x36, unsigned int)
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/* VAL_BOOL_T * */
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#define VCODEC_SET_FRAME_INFO _IOW(MFV_IOC_MAGIC, 0x37, unsigned int)
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/* VAL_FRAME_INFO_T * */
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/* #define MFV_GET_CACHECTRLADDR_CMD _IOR(MFV_IOC_MAGIC, 0x06, int) */
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extern void mmsys_cg_check(void);
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#endif /* __VCODEC_DRIVER_H__ */
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