threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
99 lines
4.5 KiB
C
99 lines
4.5 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DDP_RSZ_REG_H__
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#define __DDP_RSZ_REG_H__
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#include "ddp_reg.h"
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/* DISP_RSZ reg offset */
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#define DISP_REG_RSZ_ENABLE (0x000)
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# define FLD_RSZ_RST REG_FLD_MSB_LSB(16, 16)
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# define FLD_RSZ_EN REG_FLD_MSB_LSB(0, 0)
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#define DISP_REG_RSZ_CONTROL_1 (0x004)
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# define FLD_RSZ_INT_WCLR_EN REG_FLD_MSB_LSB(31, 31)
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# define FLD_RSZ_INTEN REG_FLD_MSB_LSB(30, 28)
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# define FLD_RSZ_DCM_DIS REG_FLD_MSB_LSB(27, 27)
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# define FLD_RSZ_VERTICAL_TABLE_SELECT REG_FLD_MSB_LSB(25, 21)
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# define FLD_RSZ_HORIZONTAL_TABLE_SELECT REG_FLD_MSB_LSB(20, 16)
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# define FLD_RSZ_LBCSON_MODE REG_FLD_MSB_LSB(9, 9)
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# define FLD_RSZ_VERTICAL_EN REG_FLD_MSB_LSB(1, 1)
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# define FLD_RSZ_HORIZONTAL_EN REG_FLD_MSB_LSB(0, 0)
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#define DISP_REG_RSZ_CONTROL_2 (0x008)
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# define FLD_RSZ_RGB_BIT_MODE REG_FLD_MSB_LSB(28, 28)
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# define FLD_RSZ_POWER_SAVING REG_FLD_MSB_LSB(9, 9)
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#define DISP_REG_RSZ_INT_FLAG (0x00c)
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# define FLD_RSZ_SOF_RESET REG_FLD_MSB_LSB(5, 5)
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# define FLD_RSZ_SIZE_ERR REG_FLD_MSB_LSB(4, 4)
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# define FLD_RSZ_FRAME_END REG_FLD_MSB_LSB(1, 1)
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# define FLD_RSZ_FRAME_START REG_FLD_MSB_LSB(0, 0)
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#define DISP_REG_RSZ_INPUT_IMAGE (0x010)
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# define FLD_RSZ_INPUT_IMAGE_H REG_FLD_MSB_LSB(31, 16)
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# define FLD_RSZ_INPUT_IMAGE_W REG_FLD_MSB_LSB(15, 0)
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#define DISP_REG_RSZ_OUTPUT_IMAGE (0x014)
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# define FLD_RSZ_OUTPUT_IMAGE_H REG_FLD_MSB_LSB(31, 16)
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# define FLD_RSZ_OUTPUT_IMAGE_W REG_FLD_MSB_LSB(15, 0)
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#define DISP_REG_RSZ_HORIZONTAL_COEFF_STEP (0x018)
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# define FLD_RSZ_HORIZONTAL_COEFF_STEP REG_FLD_MSB_LSB(22, 0)
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#define DISP_REG_RSZ_VERTICAL_COEFF_STEP (0x01c)
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# define FLD_RSZ_VERTICAL_COEFF_STEP REG_FLD_MSB_LSB(22, 0)
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#define DISP_REG_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET (0x020)
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# define FLD_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET REG_FLD_MSB_LSB(15, 0)
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#define DISP_REG_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET (0x024)
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# define FLD_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET REG_FLD_MSB_LSB(20, 0)
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#define DISP_REG_RSZ_LUMA_VERTICAL_INTEGER_OFFSET (0x028)
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# define FLD_RSZ_LUMA_VERTICAL_INTEGER_OFFSET REG_FLD_MSB_LSB(15, 0)
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#define DISP_REG_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET (0x02c)
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# define FLD_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET REG_FLD_MSB_LSB(20, 0)
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#define DISP_REG_RSZ_RSV (0x040)
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#define DISP_REG_RSZ_DEBUG_SEL (0x044)
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#define DISP_REG_RSZ_DEBUG (0x048)
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#define DISP_REG_RSZ_SHADOW_CTRL (0x0f0)
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# define FLD_RSZ_READ_WRK_REG REG_FLD_MSB_LSB(2, 2)
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# define FLD_RSZ_FORCE_COMMIT REG_FLD_MSB_LSB(1, 1)
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# define FLD_RSZ_BYPASS_SHADOW REG_FLD_MSB_LSB(0, 0)
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#define DISP_REG_RSZ_ATPG (0x0fc)
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#define DISP_REG_PAT2_GET_SET (0x200)
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#define DISP_REG_PAT2_GEN_COLOR0 (0x208)
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#define DISP_REG_PAT2_GEN_COLOR1 (0x20c)
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#define DISP_REG_PAT2_GEN_CURSOR_RB0 (0x214)
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#define DISP_REG_PAT2_GEN_CURSOR_RB1 (0x218)
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#define DISP_REG_PAT2_GEN_TILE_POS (0x224)
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#define DISP_REG_PAT2_GEN_TILE_OV (0x228)
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/* DISP_RSZ bit field */
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#define FLD_RSZ_RSV REG_FLD_MSB_LSB(31, 0)
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#define FLD_RSZ_DEBUG_SEL REG_FLD_MSB_LSB(3, 0)
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#define FLD_RSZ_DEBUG REG_FLD_MSB_LSB(31, 0)
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#define FLD_RSZ_ATPG_CT REG_FLD_MSB_LSB(1, 1)
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#define FLD_RSZ_ATPG_OB REG_FLD_MSB_LSB(0, 0)
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#define FLD_RSZ_REG2_PAT_TYPE REG_FLD_MSB_LSB(23, 16)
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#define FLD_RSZ_REG2_CURSOR_SHOW REG_FLD_MSB_LSB(1, 1)
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#define FLD_RSZ_REG2_PAT_GEN_EN REG_FLD_MSB_LSB(0, 0)
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#define FLD_RSZ_REG2_COLOR_V REG_FLD_MSB_LSB(29, 20)
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#define FLD_RSZ_REG2_COLOR_U REG_FLD_MSB_LSB(19, 10)
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#define FLD_RSZ_REG2_COLOR_Y REG_FLD_MSB_LSB(9, 0)
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#define FLD_RSZ_REG2_COLOR_A REG_FLD_MSB_LSB(7, 0)
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#define FLD_RSZ_REG2_POS_Y REG_FLD_MSB_LSB(28, 16)
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#define FLD_RSZ_REG2_POS_X REG_FLD_MSB_LSB(12, 0)
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#define FLD_RSZ_REG2_RB_CURSOR_U REG_FLD_MSB_LSB(25, 16)
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#define FLD_RSZ_REG2_RB_CURSOR_Y REG_FLD_MSB_LSB(9, 0)
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#define FLD_RSZ_REG2_RB_CURSOR_A REG_FLD_MSB_LSB(23, 16)
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#define FLD_RSZ_REG2_RB_CURSOR_V REG_FLD_MSB_LSB(9, 0)
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#define FLD_RSZ_REG2_TILE_POS_Y REG_FLD_MSB_LSB(28, 16)
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#define FLD_RSZ_REG2_TILE_POS_X REG_FLD_MSB_LSB(12, 0)
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#define FLD_RSZ_REG2_TILE_OV_Y REG_FLD_MSB_LSB(15, 8)
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#define FLD_RSZ_REG2_TILE_OV_X REG_FLD_MSB_LSB(7, 0)
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#endif
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