threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
156 lines
3.2 KiB
C
156 lines
3.2 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _H_DDP_HAL_
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#define _H_DDP_HAL_
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/* DISP Mutex */
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#define DISP_MUTEX_TOTAL (12)
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#define DISP_MUTEX_DDP_FIRST (0)
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/* modify from 4 to 3, cause 4 is used for OVL0/OVL1 SW trigger */
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#define DISP_MUTEX_DDP_LAST (3)
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#define DISP_MUTEX_DDP_COUNT (DISP_MUTEX_DDP_LAST - DISP_MUTEX_DDP_FIRST + 1)
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#define DISP_MUTEX_MDP_FIRST (DISP_MUTEX_DDP_LAST + 1)
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#define DISP_MUTEX_MDP_COUNT (3)
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#define __DISP_MUTEX_INT_MSK ((1 << (DISP_MUTEX_DDP_COUNT)) - 1)
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#define DISP_MUTEX_INT_MSK \
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((__DISP_MUTEX_INT_MSK << DISP_MUTEX_TOTAL) | __DISP_MUTEX_INT_MSK)
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/* DISP MODULE */
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enum DISP_MODULE_ENUM {
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DISP_MODULE_OVL0 = 0, /* must start from 0 */
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DISP_MODULE_OVL0_2L,
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DISP_MODULE_OVL1_2L,
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DISP_MODULE_RDMA0,
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DISP_MODULE_RDMA1,
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DISP_MODULE_RDMA_VIRTUAL0,
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DISP_MODULE_WDMA0,
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DISP_MODULE_WDMA_VIRTUAL0,
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DISP_MODULE_WDMA_VIRTUAL1,
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DISP_MODULE_COLOR0,
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DISP_MODULE_CCORR0,
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DISP_MODULE_AAL0,
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DISP_MODULE_GAMMA0,
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DISP_MODULE_DITHER0,
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DISP_MODULE_DSI0,
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DISP_MODULE_DSI1,
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DISP_MODULE_DSIDUAL,
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DISP_MODULE_PWM0,
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DISP_MODULE_CONFIG,
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DISP_MODULE_MUTEX,
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DISP_MODULE_SMI_COMMON,
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DISP_MODULE_SMI_LARB0,
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DISP_MODULE_SMI_LARB1,
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DISP_MODULE_MIPI0,
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DISP_MODULE_MIPI1,
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DISP_MODULE_RSZ0,
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DISP_MODULE_DPI,
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DISP_MODULE_DPI_VIRTUAL,
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DISP_MODULE_POSTMASK,
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DISP_MODULE_UNKNOWN,
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DISP_MODULE_NUM
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};
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/* DISP MODULE */
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enum DISP_MODULE_TYPE_ENUM {
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DISP_T_OVL = 0, /* must start from 0 */
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DISP_T_RSZ,
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DISP_T_RDMA,
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DISP_T_WDMA,
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DISP_T_COLOR,
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DISP_T_CCORR, /* 5 */
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DISP_T_AAL,
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DISP_T_GAMMA,
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DISP_T_DITHER,
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DISP_T_SPLIT,
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DISP_T_DSI, /* 10 */
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DISP_T_DPI,
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DISP_T_DBI,
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DISP_T_PWM,
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DISP_T_POSTMASK,
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DISP_T_UNKNOWN,
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DISP_T_NUM,
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};
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enum dst_module_type {
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DST_MOD_REAL_TIME,
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DST_MOD_WDMA,
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};
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enum DISP_SLOT_ENUM {
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DISP_SLOT_IS_DC,
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DISP_SLOT_OVL0_BW,
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DISP_SLOT_OVL0_FBDC_BW,
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DISP_SLOT_OVL0_2L_BW,
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DISP_SLOT_OVL0_2L_FBDC_BW,
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DISP_SLOT_RDMA0_BW,
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DISP_SLOT_WDMA0_BW,
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DISP_SLOT_OVL0_LASTF_BW,
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DISP_SLOT_OVL0_2L_LASTF_BW,
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DISP_SLOT_NUM,
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};
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enum OVL_LAYER_SOURCE {
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OVL_LAYER_SOURCE_MEM = 0,
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OVL_LAYER_SOURCE_RESERVED = 1,
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OVL_LAYER_SOURCE_SCL = 2,
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OVL_LAYER_SOURCE_PQ = 3,
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};
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enum OVL_LAYER_SECURE_MODE {
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OVL_LAYER_NORMAL_BUFFER = 0,
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OVL_LAYER_SECURE_BUFFER = 1,
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OVL_LAYER_PROTECTED_BUFFER = 2
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};
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enum CMDQ_SWITCH {
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CMDQ_DISABLE = 0,
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CMDQ_ENABLE
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};
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enum CMDQ_STATE {
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CMDQ_WAIT_LCM_TE,
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CMDQ_BEFORE_STREAM_SOF,
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CMDQ_WAIT_STREAM_EOF_EVENT,
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CMDQ_CHECK_IDLE_AFTER_STREAM_EOF,
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CMDQ_AFTER_STREAM_EOF,
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CMDQ_ESD_CHECK_READ,
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CMDQ_ESD_CHECK_CMP,
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CMDQ_ESD_ALLC_SLOT,
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CMDQ_ESD_FREE_SLOT,
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CMDQ_STOP_VDO_MODE,
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CMDQ_START_VDO_MODE,
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CMDQ_DSI_RESET,
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CMDQ_AFTER_STREAM_SOF,
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CMDQ_DSI_LFR_MODE,
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CMDQ_RESET_AFTER_STREAM_EOF,
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CMDQ_BDG_REG_READ,
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};
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enum DDP_IRQ_LEVEL {
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DDP_IRQ_LEVEL_ALL = 0,
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DDP_IRQ_LEVEL_NONE,
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DDP_IRQ_LEVEL_ERROR
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};
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#endif /* _H_DDP_HAL_ */
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