threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
129 lines
3.0 KiB
C
129 lines
3.0 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __USB20_H__
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#define __USB20_H__
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#ifdef CONFIG_FPGA_EARLY_PORTING
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#define FPGA_PLATFORM
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#endif
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struct mt_usb_work {
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struct delayed_work dwork;
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int ops;
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};
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struct mt_usb_glue {
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struct device *dev;
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struct platform_device *musb;
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};
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#define glue_to_musb(g) platform_get_drvdata(g->musb)
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extern unsigned int upmu_get_rgs_chrdet(void);
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extern bool upmu_is_chr_det(void);
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extern enum charger_type mt_charger_type_detection(void);
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extern void BATTERY_SetUSBState(int usb_state);
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extern void upmu_interrupt_chrdet_int_en(unsigned int val);
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/* specific USB fuctnion */
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enum CABLE_MODE {
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CABLE_MODE_CHRG_ONLY = 0,
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CABLE_MODE_NORMAL,
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CABLE_MODE_HOST_ONLY,
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CABLE_MODE_MAX
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};
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enum USB_CLK_STATE {
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NO_CHANGE = 0,
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ON_TO_OFF,
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OFF_TO_ON,
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};
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/* specific USB operation */
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enum CONNECTION_OPS {
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CONNECTION_OPS_DISC = 0,
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CONNECTION_OPS_CHECK,
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CONNECTION_OPS_CONN
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};
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enum VBUS_OPS {
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VBUS_OPS_OFF = 0,
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VBUS_OPS_ON
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};
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enum MTK_USB_SMC_CALL {
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MTK_USB_SMC_INFRA_REQUEST = 0,
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MTK_USB_SMC_INFRA_RELEASE,
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MTK_USB_SMC_NUM
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};
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#ifdef CONFIG_MTK_UART_USB_SWITCH
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enum PORT_MODE {
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PORT_MODE_USB = 0,
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PORT_MODE_UART,
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PORT_MODE_MAX
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};
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extern bool usb_phy_check_in_uart_mode(void);
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extern void usb_phy_switch_to_usb(void);
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extern void usb_phy_switch_to_uart(void);
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#endif
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#ifdef FPGA_PLATFORM
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extern void USB_PHY_Write_Register8(u8 var, u8 addr);
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extern u8 USB_PHY_Read_Register8(u8 addr);
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#endif
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extern struct clk *musb_clk;
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extern struct clk *musb_ref_clk;
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extern struct clk *musb_clk_top_sel;
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extern struct clk *musb_clk_univpll5_d4;
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#ifdef CONFIG_MTK_UART_USB_SWITCH
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#define RG_GPIO_SELECT (0x600)
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#define GPIO_SEL_OFFSET (4)
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#define GPIO_SEL_MASK (0x7 << GPIO_SEL_OFFSET)
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#define GPIO_SEL_UART0 (0x1 << GPIO_SEL_OFFSET)
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#define GPIO_SEL_UART1 (0x2 << GPIO_SEL_OFFSET)
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#define GET_GPIO_SEL_VAL(x) ((x & GPIO_SEL_MASK) >> GPIO_SEL_OFFSET)
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extern void __iomem *ap_gpio_base;
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extern bool in_uart_mode;
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#endif
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extern int usb20_phy_init_debugfs(void);
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extern enum charger_type mt_get_charger_type(void);
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#ifndef CONFIG_FPGA_EARLY_PORTING
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#include <upmu_common.h>
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#endif
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#define PHY_IDLE_MODE 0
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#define PHY_DEV_ACTIVE 1
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#define PHY_HOST_ACTIVE 2
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void set_usb_phy_mode(int mode);
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#ifdef CONFIG_USB_MTK_OTG
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extern bool usb20_check_vbus_on(void);
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#endif
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extern bool usb_prepare_clock(bool enable);
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extern void usb_prepare_enable_clock(bool enable);
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/* usb host mode wakeup */
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#define USB_WK_CTRL 0x420
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#define USB_CDEN BIT(6)
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#define USB_IP_SLEEP BIT(12)
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#define USB_CDDEBOUNCE(x) (((x) & 0xf) << 28)
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#define MISC_CONFIG 0xf08
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#define USB_CD_CLR BIT(7)
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#endif
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