threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifdef CONFIG_MTK_MUSBFSH_QMU_SUPPORT
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include <linux/stat.h>
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#include "musbfsh_core.h"
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#include "musbfsh_host.h"
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#include "musbfsh_hsdma.h"
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/*#include "mtk_musb.h"*/
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#include "musbfsh_qmu.h"
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#include "mtk11_qmu.h"
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void __iomem *musbfsh_qmu_base;
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/* debug variable to check musbfsh_qmu_base issue */
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void __iomem *musbfsh_qmu_base_2;
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int musbfsh_qmu_init(struct musbfsh *musbfsh)
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{
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/* set DMA channel 0 burst mode to boost QMU speed */
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musbfsh_writel(musbfsh->mregs, 0x204,
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musbfsh_readl(musbfsh->mregs, 0x204) | 0x600);
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musbfsh_writel((musbfsh->mregs + MUSBFSH_QISAR), 0x30, 0);
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#ifdef CONFIG_OF
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musbfsh_qmu_base = (void __iomem *)(musbfsh->mregs + MUSBFSH_QMUBASE);
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/* debug variable to check musbfsh_qmu_base issue */
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musbfsh_qmu_base_2 = (void __iomem *)(musbfsh->mregs + MUSBFSH_QMUBASE);
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#else
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musbfsh_qmu_base = (void __iomem *)(musbfsh->mregs + MUSBFSH_QMUBASE);
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/* debug variable to check musbfsh_qmu_base issue */
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musbfsh_qmu_base_2 = (void __iomem *)(musbfsh->mregs + MUSBFSH_QMUBASE);
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#endif
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mb(); /* */
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if (mtk11_qmu_init_gpd_pool(musbfsh->controller)) {
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QMU_ERR("[QMU]mtk11_qmu_init_gpd_pool fail\n");
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return -1;
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}
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return 0;
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}
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void musbfsh_qmu_exit(struct musbfsh *musbfsh)
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{
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mtk11_qmu_destroy_gpd_pool(musbfsh->controller);
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}
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void musbfsh_disable_q_all(struct musbfsh *musbfsh)
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{
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u32 ep_num;
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QMU_WARN("disable_q_all\n");
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for (ep_num = 1; ep_num <= RXQ_NUM; ep_num++) {
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if (mtk11_is_qmu_enabled(ep_num, RXQ))
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mtk11_disable_q(musbfsh, ep_num, 1);
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}
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for (ep_num = 1; ep_num <= TXQ_NUM; ep_num++) {
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if (mtk11_is_qmu_enabled(ep_num, TXQ))
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mtk11_disable_q(musbfsh, ep_num, 0);
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}
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}
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irqreturn_t musbfsh_q_irq(struct musbfsh *musbfsh)
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{
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irqreturn_t retval = IRQ_NONE;
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u32 wQmuVal = musbfsh->int_queue;
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u32 i;
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QMU_ERR("wQmuVal:%d\n", wQmuVal);
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for (i = 1; i <= MAX_QMU_EP; i++) {
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if (wQmuVal & DQMU_M_RX_DONE(i))
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h_mtk11_qmu_done_rx(musbfsh, i);
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if (wQmuVal & DQMU_M_TX_DONE(i))
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h_mtk11_qmu_done_tx(musbfsh, i);
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}
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mtk11_qmu_irq_err(musbfsh, wQmuVal);
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return retval;
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}
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void musbfsh_flush_qmu(u32 ep_num, u8 isRx)
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{
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QMU_DBG("flush %s(%d)\n", isRx ? "RQ" : "TQ", ep_num);
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mtk11_qmu_stop(ep_num, isRx);
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mtk11_qmu_reset_gpd_pool(ep_num, isRx);
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}
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void musbfsh_restart_qmu(struct musbfsh *musbfsh, u32 ep_num, u8 isRx)
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{
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QMU_DBG("restart %s(%d)\n", isRx ? "RQ" : "TQ", ep_num);
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mtk11_flush_ep_csr(musbfsh, ep_num, isRx);
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mtk11_qmu_enable(musbfsh, ep_num, isRx);
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}
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bool musbfsh_is_qmu_stop(u32 ep_num, u8 isRx)
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{
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void __iomem *base = musbfsh_qmu_base;
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/* debug variable to check musbfsh_qmu_base issue */
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if (musbfsh_qmu_base != musbfsh_qmu_base_2) {
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QMU_WARN("musbfsh_qmu_base != musbfsh_qmu_base_2");
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QMU_WARN("musbfsh_qmu_base = %p, musbfsh_qmu_base_2=%p",
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musbfsh_qmu_base, musbfsh_qmu_base_2);
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}
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if (!isRx) {
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if (MGC_ReadQMU16(base, MGC_O_QMU_TQCSR(ep_num))
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& DQMU_QUE_ACTIVE)
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return false;
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else
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return true;
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} else {
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if (MGC_ReadQMU16(base, MGC_O_QMU_RQCSR(ep_num))
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& DQMU_QUE_ACTIVE)
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return false;
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else
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return true;
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}
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}
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void musbfsh_tx_zlp_qmu(struct musbfsh *musbfsh, u32 ep_num)
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{
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/* sent ZLP through PIO */
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void __iomem *epio = musbfsh->endpoints[ep_num].regs;
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void __iomem *mbase = musbfsh->mregs;
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int cnt = 50; /* 50*200us, total 10 ms */
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int is_timeout = 1;
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u16 csr;
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QMU_WARN("TX ZLP direct sent\n");
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musbfsh_ep_select(mbase, ep_num);
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/* disable dma for pio */
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csr = musbfsh_readw(epio, MUSBFSH_TXCSR);
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csr &= ~MUSBFSH_TXCSR_DMAENAB;
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musbfsh_writew(epio, MUSBFSH_TXCSR, csr);
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/* TXPKTRDY */
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csr = musbfsh_readw(epio, MUSBFSH_TXCSR);
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csr |= MUSBFSH_TXCSR_TXPKTRDY;
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musbfsh_writew(epio, MUSBFSH_TXCSR, csr);
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/* wait ZLP sent */
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while (cnt--) {
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csr = musbfsh_readw(epio, MUSBFSH_TXCSR);
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if (!(csr & MUSBFSH_TXCSR_TXPKTRDY)) {
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is_timeout = 0;
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break;
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}
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udelay(200);
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}
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/* re-enable dma for qmu */
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csr = musbfsh_readw(epio, MUSBFSH_TXCSR);
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csr |= MUSBFSH_TXCSR_DMAENAB;
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musbfsh_writew(epio, MUSBFSH_TXCSR, csr);
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if (is_timeout)
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QMU_ERR("TX ZLP sent fail???\n");
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QMU_WARN("TX ZLP sent done\n");
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}
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int mtk11_kick_CmdQ(struct musbfsh *musbfsh, int isRx,
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struct musbfsh_qh *qh, struct urb *urb)
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{
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void __iomem *mbase = musbfsh->mregs;
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u16 intr_e = 0;
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struct musbfsh_hw_ep *hw_ep = qh->hw_ep;
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void __iomem *epio = hw_ep->regs;
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unsigned int offset = 0;
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u8 bIsIoc;
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u8 *pBuffer;
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u32 dwLength;
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u16 i;
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u32 gdp_free_count = 0;
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if (!urb) {
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QMU_WARN("!urb\n");
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return -1; /*KOBE : should we return a value */
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}
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if (!mtk11_is_qmu_enabled(hw_ep->epnum, isRx)) {
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INFO("! mtk_is_qmu_enabled\n");
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musbfsh_ep_select(mbase, hw_ep->epnum);
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mtk11_flush_ep_csr(musbfsh, hw_ep->epnum, isRx);
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if (isRx) {
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INFO("isRX = 1\n");
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if (qh->type == USB_ENDPOINT_XFER_ISOC) {
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INFO("USB_ENDPOINT_XFER_ISOC\n");
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if (qh->hb_mult == 3)
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musbfsh_writew(epio,
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MUSBFSH_RXMAXP,
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qh->maxpacket|0x1000);
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else if (qh->hb_mult == 2)
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musbfsh_writew(epio,
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MUSBFSH_RXMAXP,
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qh->maxpacket|0x800);
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else
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musbfsh_writew(epio,
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MUSBFSH_RXMAXP, qh->maxpacket);
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} else {
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INFO("!! USB_ENDPOINT_XFER_ISOC\n");
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musbfsh_writew(epio, MUSBFSH_RXMAXP,
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qh->maxpacket);
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}
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musbfsh_writew(epio, MUSBFSH_RXCSR,
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MUSBFSH_RXCSR_DMAENAB);
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/*CC: speed */
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musbfsh_writeb(epio, MUSBFSH_RXTYPE, qh->type_reg);
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musbfsh_writeb(epio, MUSBFSH_RXINTERVAL, qh->intv_reg);
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if (musbfsh->is_multipoint) {
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INFO("is_multipoint\n");
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musbfsh_write_rxfunaddr(musbfsh->mregs,
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hw_ep->epnum, qh->addr_reg);
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musbfsh_write_rxhubaddr(musbfsh->mregs,
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hw_ep->epnum, qh->h_addr_reg);
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musbfsh_write_rxhubport(musbfsh->mregs,
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hw_ep->epnum, qh->h_port_reg);
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} else {
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INFO("!! is_multipoint\n");
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musbfsh_writeb(musbfsh->mregs,
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MUSBFSH_FADDR, qh->addr_reg);
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}
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/*turn off intrRx*/
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intr_e = musbfsh_readw(musbfsh->mregs, MUSBFSH_INTRRXE);
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intr_e = intr_e & (~(1<<(hw_ep->epnum)));
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musbfsh_writew(musbfsh->mregs, MUSBFSH_INTRRXE, intr_e);
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} else {
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musbfsh_writew(epio, MUSBFSH_TXMAXP,
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qh->maxpacket);
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musbfsh_writew(epio, MUSBFSH_TXCSR,
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MUSBFSH_TXCSR_DMAENAB);
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/*CC: speed?*/
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musbfsh_writeb(epio, MUSBFSH_TXTYPE, qh->type_reg);
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musbfsh_writeb(epio, MUSBFSH_TXINTERVAL, qh->intv_reg);
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if (musbfsh->is_multipoint) {
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INFO("is_multipoint\n");
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musbfsh_write_txfunaddr(mbase,
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hw_ep->epnum, qh->addr_reg);
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musbfsh_write_txhubaddr(mbase,
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hw_ep->epnum, qh->h_addr_reg);
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musbfsh_write_txhubport(mbase,
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hw_ep->epnum, qh->h_port_reg);
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/* FIXME if !epnum, do the same for RX ... */
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} else {
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INFO("!! is_multipoint\n");
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musbfsh_writeb(mbase, MUSBFSH_FADDR,
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qh->addr_reg);
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}
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/* turn off intrTx , but this will be
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*revert by musbfsh_ep_program
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*/
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intr_e = musbfsh_readw(musbfsh->mregs, MUSBFSH_INTRTXE);
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intr_e = intr_e & (~(1<<hw_ep->epnum));
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musbfsh_writew(musbfsh->mregs, MUSBFSH_INTRTXE, intr_e);
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}
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INFO("mtk11_qmu_enable\n");
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mtk11_qmu_enable(musbfsh, hw_ep->epnum, isRx);
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}
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gdp_free_count = mtk11_qmu_free_gpd_count(isRx, hw_ep->epnum);
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if (qh->type == USB_ENDPOINT_XFER_ISOC) {
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INFO("USB_ENDPOINT_XFER_ISOC\n");
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pBuffer = (uint8_t *)urb->transfer_dma;
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if (gdp_free_count < urb->number_of_packets) {
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INFO("gdp_free_count:%d, number_of_packets:%d\n",
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gdp_free_count, urb->number_of_packets);
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musbfsh_bug();
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}
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for (i = 0; i < urb->number_of_packets; i++) {
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urb->iso_frame_desc[i].status = 0;
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offset = urb->iso_frame_desc[i].offset;
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dwLength = urb->iso_frame_desc[i].length;
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/* If interrupt on complete ? */
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bIsIoc = (i == (urb->number_of_packets-1)) ? 1 : 0;
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INFO("mtk11_qmu_insert_task\n");
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mtk11_qmu_insert_task(hw_ep->epnum,
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isRx, pBuffer+offset, dwLength, 0, bIsIoc);
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mtk11_qmu_resume(hw_ep->epnum, isRx);
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}
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if (mtk11_host_qmu_max_active_isoc_gpd <
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mtk11_qmu_used_gpd_count(isRx, hw_ep->epnum))
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mtk11_host_qmu_max_active_isoc_gpd =
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mtk11_qmu_used_gpd_count(isRx, hw_ep->epnum);
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if (mtk11_host_qmu_number_pkts < urb->number_of_packets)
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mtk11_host_qmu_number_pkts =
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urb->number_of_packets;
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{
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static DEFINE_RATELIMIT_STATE(ratelimit, 1 * HZ, 1);
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static int skip_cnt;
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if (__ratelimit(&ratelimit)) {
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INFO(
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"max_isoc gpd:%d max_pkts:%d skip_cnt:%d\n",
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mtk11_host_qmu_max_active_isoc_gpd,
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mtk11_host_qmu_number_pkts,
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skip_cnt);
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skip_cnt = 0;
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} else
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skip_cnt++;
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}
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} else {
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/* Must be the bulk transfer type */
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QMU_WARN("non isoc\n");
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pBuffer = (uint8_t *)urb->transfer_dma;
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if (urb->transfer_buffer_length < QMU_RX_SPLIT_THRE) {
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if (gdp_free_count < 1) {
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INFO(
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"gdp_free_count:%d, number_of_packets:%d\n",
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gdp_free_count, urb->number_of_packets);
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musbfsh_bug();
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}
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INFO("urb->transfer_buffer_length : %d\n",
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urb->transfer_buffer_length);
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dwLength = urb->transfer_buffer_length;
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bIsIoc = 1;
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mtk11_qmu_insert_task(hw_ep->epnum,
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isRx, pBuffer+offset, dwLength, 0, bIsIoc);
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mtk11_qmu_resume(hw_ep->epnum, isRx);
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} else {
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/*reuse isoc urb->unmber_of_packets*/
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urb->number_of_packets =
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((urb->transfer_buffer_length) +
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QMU_RX_SPLIT_BLOCK_SIZE-1)/
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(QMU_RX_SPLIT_BLOCK_SIZE);
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if (gdp_free_count < urb->number_of_packets) {
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INFO(
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"gpd_free_count:%d, number_of_packets:%d\n",
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gdp_free_count, urb->number_of_packets);
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musbfsh_bug();
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}
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for (i = 0; i < urb->number_of_packets; i++) {
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offset = QMU_RX_SPLIT_BLOCK_SIZE*i;
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dwLength = QMU_RX_SPLIT_BLOCK_SIZE;
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/* If interrupt on complete ? */
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bIsIoc = (i == (urb->number_of_packets-1)) ?
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1 : 0;
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dwLength = (i == (urb->number_of_packets-1)) ?
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((urb->transfer_buffer_length)
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% QMU_RX_SPLIT_BLOCK_SIZE) : dwLength;
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if (dwLength == 0)
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dwLength = QMU_RX_SPLIT_BLOCK_SIZE;
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mtk11_qmu_insert_task(hw_ep->epnum, isRx,
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pBuffer+offset, dwLength, 0, bIsIoc);
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mtk11_qmu_resume(hw_ep->epnum, isRx);
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}
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}
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}
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INFO("\n");
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return 0;
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}
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#endif
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