threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
4.4 KiB
C
108 lines
4.4 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __SSPM_IPI_MBOX_LAYOUT_H__
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#define __SSPM_IPI_MBOX_LAYOUT_H__
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#define IPI_MBOX_TOTAL 4
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#define IPI_MBOX0_64D 0
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#define IPI_MBOX1_64D 0
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#define IPI_MBOX2_64D 0
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#define IPI_MBOX3_64D 0
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#define IPI_MBOX4_64D 0
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#define IPI_MBOX_MODE ((IPI_MBOX4_64D<<4)|(IPI_MBOX3_64D<<3)| \
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(IPI_MBOX2_64D<<2)|(IPI_MBOX1_64D<<1)| \
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IPI_MBOX0_64D)
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#define IPI_MBOX0_SLOTS ((IPI_MBOX0_64D+1)*32)
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#define IPI_MBOX1_SLOTS ((IPI_MBOX1_64D+1)*32)
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#define IPI_MBOX2_SLOTS ((IPI_MBOX2_64D+1)*32)
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#define IPI_MBOX3_SLOTS ((IPI_MBOX3_64D+1)*32)
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#define IPI_MBOX4_SLOTS ((IPI_MBOX4_64D+1)*32)
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/* definition of slot size for send PINs */
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#define PINS_SIZE_PLATFORM 3 /* the following will use mbox 0 */
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#define PINS_SIZE_CPU_DVFS 4
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#if defined(CONFIG_MACH_MT6768) || defined(CONFIG_MACH_MT6771)
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#define PINS_SIZE_QOS 4
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#else
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#define PINS_SIZE_QOS 6
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#endif
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#define PINS_SIZE_TST1 4
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#define PINS_SIZE_FHCTL 9
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#define PINS_SIZE_SMI 3
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/* ============================================================ */
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#define PINS_SIZE_MCDI 2 /* the following will use mbox 1 */
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#define PINS_SIZE_SPM_SUSPEND 8
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#define PINS_SIZE_PMIC 5
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#define PINS_SIZE_PPM 7
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#define PINS_SIZE_THERMAL 4
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#define PINS_SIZE_UPOWER 4
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#define PINS_SIZE_CM 2
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/* ============================================================ */
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/* definition of slot offset for PINs */
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#define PINS_OFFSET_PLATFORM 0 /* the following will use mbox 0 */
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#define PINS_OFFSET_CPU_DVFS (PINS_OFFSET_PLATFORM + PINS_SIZE_PLATFORM)
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#define PINS_OFFSET_QOS (PINS_OFFSET_CPU_DVFS + PINS_SIZE_CPU_DVFS)
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#define PINS_OFFSET_TST1 (PINS_OFFSET_QOS + PINS_SIZE_QOS)
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#define PINS_OFFSET_FHCTL (PINS_OFFSET_TST1 + PINS_SIZE_TST1)
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#define PINS_OFFSET_SMI (PINS_OFFSET_FHCTL + PINS_SIZE_FHCTL)
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#define PINS_MBOX0_USED (PINS_OFFSET_SMI + PINS_SIZE_SMI)
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#if (PINS_MBOX0_USED > IPI_MBOX0_SLOTS)
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#error "MBOX0 cannot hold all pin definitions"
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#endif
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/* ============================================================ */
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#define PINS_OFFSET_MCDI 0 /* the following will use mbox 1 */
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#define PINS_OFFSET_SPM_SUSPEND (PINS_OFFSET_MCDI + PINS_SIZE_MCDI)
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#define PINS_OFFSET_PMIC (PINS_OFFSET_SPM_SUSPEND + \
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PINS_SIZE_SPM_SUSPEND)
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#define PINS_OFFSET_PPM (PINS_OFFSET_PMIC + PINS_SIZE_PMIC)
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#define PINS_OFFSET_THERMAL (PINS_OFFSET_PPM + PINS_SIZE_PPM)
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#define PINS_OFFSET_UPOWER (PINS_OFFSET_THERMAL + PINS_SIZE_THERMAL)
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#define PINS_OFFSET_CM (PINS_OFFSET_UPOWER + PINS_SIZE_UPOWER)
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#define PINS_MBOX1_USED (PINS_OFFSET_CM + PINS_SIZE_CM)
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#if (PINS_MBOX1_USED > IPI_MBOX1_SLOTS)
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#error "MBOX1 cannot hold all pin definitions"
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#endif
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/* ============================================================ */
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/* definition of slot size for received PINs */
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#define PINR_SIZE_PLATFORM 3 /* the following will use mbox 2 */
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#define PINR_SIZE_CPU_DVFS 4
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#if defined(CONFIG_MACH_MT6768) || defined(CONFIG_MACH_MT6771)
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#define PINR_SIZE_QOS 4
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#else
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#define PINR_SIZE_QOS 6
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#endif
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#define PINR_SIZE_TST1 4
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/* definition of slot offset for PINs */
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#define PINR_OFFSET_PLATFORM 0 /* the following will use mbox 2 */
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#define PINR_OFFSET_CPU_DVFS (PINR_OFFSET_PLATFORM + PINR_SIZE_PLATFORM)
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#define PINR_OFFSET_QOS (PINR_OFFSET_CPU_DVFS + PINR_SIZE_CPU_DVFS)
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#define PINR_OFFSET_TST1 (PINR_OFFSET_QOS + PINR_SIZE_QOS)
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#define PINR_MBOX2_USED (PINR_OFFSET_TST1 + PINR_SIZE_TST1)
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#if (PINR_MBOX2_USED > IPI_MBOX2_SLOTS)
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#error "MBOX2 cannot hold all pin definitions"
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#endif
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#define SHAREMBOX_NO_MCDI 3
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#define SHAREMBOX_OFFSET_MCDI 0
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#define SHAREMBOX_SIZE_MCDI 20
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#define SHAREMBOX_OFFSET_TIMESTAMP (SHAREMBOX_OFFSET_MCDI + \
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SHAREMBOX_SIZE_MCDI)
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#define SHAREMBOX_SIZE_TIMESTAMP 6
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#endif /* __SSPM_IPI_MBOX_LAYOUT_H__ */
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