threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
213 lines
7.4 KiB
C
213 lines
7.4 KiB
C
/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SMI_CONF_H__
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#define __SMI_CONF_H__
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#include <soc/mediatek/smi.h>
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#include "smi_hw.h"
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#include "../smi_reg.h"
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#include "../smi_conf_dbg.h"
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#define SMI_SCEN_NUM (2)
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#define SMI_ESL_INIT (0)
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#define SMI_ESL_VPWFD (SMI_ESL_INIT)
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#define SMI_ESL_ICFP (1)
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#define SMI_ESL_VR4K (SMI_ESL_INIT)
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static u32 smi_scen_map[SMI_BWC_SCEN_CNT] = {
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_VPWFD, SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K,
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SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_INIT
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};
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static u32 smi_larb_cmd_gp_en_port[SMI_LARB_NUM][2] = {
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{0, 5}, {0, 0}, {0, 0}, {0, 0},
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};
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static u32 smi_larb_bw_thrt_en_port[SMI_LARB_NUM][2] = { /* non-HRT */
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{4, SMI_LARB0_PORT_NUM}, {0, SMI_LARB1_PORT_NUM},
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{0, SMI_LARB2_PORT_NUM}, {0, 0},
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};
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/* conf */
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#define SMI_COMM_CONF_NUM (8)
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struct mtk_smi_pair smi_comm_conf_pair[SMI_COMM_CONF_NUM] = {
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{SMI_L1LEN, 0xb},
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{SMI_WRR_REG0, 0x30c30c},
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{SMI_DCM, 0x4fd},
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{SMI_Mx_RWULTRA_WRRy(1, 0, 0), 0x30c30c},
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{SMI_Mx_RWULTRA_WRRy(1, 1, 0), 0x30c30c},
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{SMI_Mx_RWULTRA_WRRy(2, 0, 0), 0x30c30c},
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{SMI_Mx_RWULTRA_WRRy(2, 1, 0), 0x30c30c},
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{SMI_DUMMY, 0x1},
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};
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#define SMI_LARB0_CONF_NUM (8)
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struct mtk_smi_pair smi_larb0_conf_pair[SMI_LARB0_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370223},
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{SMI_LARB_SW_FLAG, 0x1},
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{SMI_LARB_SPM_ULTRA_MASK, 0xffffffc0},
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{SMI_LARB_WRR_PORT(0), 0xb},
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{SMI_LARB_WRR_PORT(1), 0xb},
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{SMI_LARB_WRR_PORT(2), 0xb},
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{SMI_LARB_WRR_PORT(3), 0xb},
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{SMI_LARB_WRR_PORT(4), 0xb},
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};
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#define SMI_LARB1_CONF_NUM (2)
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struct mtk_smi_pair smi_larb1_conf_pair[SMI_LARB1_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370223},
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{SMI_LARB_SW_FLAG, 0x1},
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};
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#define SMI_LARB2_CONF_NUM (3)
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struct mtk_smi_pair smi_larb2_conf_pair[SMI_LARB2_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370223},
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{SMI_LARB_SW_FLAG, 0x1},
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{SMI_LARB_SPM_ULTRA_MASK, 0xffffc000},
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};
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u32 smi_conf_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_CONF_NUM, SMI_LARB1_CONF_NUM,
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SMI_LARB2_CONF_NUM, SMI_LARB1_CONF_NUM,
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SMI_COMM_CONF_NUM,
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};
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struct mtk_smi_pair *smi_conf_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_conf_pair, smi_larb1_conf_pair,
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smi_larb2_conf_pair, smi_larb1_conf_pair,
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smi_comm_conf_pair,
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};
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/* scen: INIT */
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struct mtk_smi_pair smi_comm_init_pair[SMI_LARB_NUM] = {
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{SMI_L1ARB(0), 0x1ba5}, {SMI_L1ARB(1), 0x1000},
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{SMI_L1ARB(2), 0x15d3}, {SMI_L1ARB(3), 0x1000},
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};
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struct mtk_smi_pair smi_larb0_init_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x1f},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0x7},
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{SMI_LARB_OSTDL_PORT(4), 0x7}, {SMI_LARB_OSTDL_PORT(5), 0x4},
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{SMI_LARB_OSTDL_PORT(6), 0x4}, {SMI_LARB_OSTDL_PORT(7), 0x1f},
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};
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struct mtk_smi_pair smi_larb1_init_pair[SMI_LARB1_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x3}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x1}, {SMI_LARB_OSTDL_PORT(3), 0x1},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x5},
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{SMI_LARB_OSTDL_PORT(6), 0x3}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x6},
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};
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struct mtk_smi_pair smi_larb2_init_pair[SMI_LARB2_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0xc}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x4}, {SMI_LARB_OSTDL_PORT(3), 0x4},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x1}, {SMI_LARB_OSTDL_PORT(11), 0x1},
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};
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struct mtk_smi_pair smi_larb3_init_pair[SMI_LARB3_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x16}, {SMI_LARB_OSTDL_PORT(1), 0x14},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x2}, {SMI_LARB_OSTDL_PORT(5), 0x2},
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{SMI_LARB_OSTDL_PORT(6), 0x4}, {SMI_LARB_OSTDL_PORT(7), 0x2},
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{SMI_LARB_OSTDL_PORT(8), 0x2}, {SMI_LARB_OSTDL_PORT(9), 0x2},
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{SMI_LARB_OSTDL_PORT(10), 0x2}, {SMI_LARB_OSTDL_PORT(11), 0x2},
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{SMI_LARB_OSTDL_PORT(12), 0x4}, {SMI_LARB_OSTDL_PORT(13), 0x4},
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{SMI_LARB_OSTDL_PORT(14), 0x4}, {SMI_LARB_OSTDL_PORT(15), 0x2},
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{SMI_LARB_OSTDL_PORT(16), 0x2}, {SMI_LARB_OSTDL_PORT(17), 0x2},
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{SMI_LARB_OSTDL_PORT(18), 0x2}, {SMI_LARB_OSTDL_PORT(19), 0x2},
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{SMI_LARB_OSTDL_PORT(20), 0x2},
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};
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/* scen: ICFP */
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struct mtk_smi_pair smi_comm_icfp_pair[SMI_LARB_NUM] = {
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{SMI_L1ARB(0), 0x1327}, {SMI_L1ARB(1), 0x119e},
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{SMI_L1ARB(2), 0x1241}, {SMI_L1ARB(3), 0x12e6},
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};
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struct mtk_smi_pair smi_larb0_icfp_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x1f},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0x7},
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{SMI_LARB_OSTDL_PORT(4), 0x7}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0xb}, {SMI_LARB_OSTDL_PORT(7), 0x1f},
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};
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/* {mdp_wdma0(5), 0x4}, {mdp_wrot0(6), 0x4} */
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struct mtk_smi_pair smi_larb2_icfp_pair[SMI_LARB2_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x6}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x3},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x1}, {SMI_LARB_OSTDL_PORT(11), 0x1},
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};
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/* {imgi(0), 0xc}, {img3o(2), 0x4}, {vipi(3), 0x4} */
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struct mtk_smi_pair smi_larb3_icfp_pair[SMI_LARB3_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x14}, {SMI_LARB_OSTDL_PORT(1), 0x6},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x2}, {SMI_LARB_OSTDL_PORT(5), 0x2},
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{SMI_LARB_OSTDL_PORT(6), 0x4}, {SMI_LARB_OSTDL_PORT(7), 0x2},
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{SMI_LARB_OSTDL_PORT(8), 0x2}, {SMI_LARB_OSTDL_PORT(9), 0x2},
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{SMI_LARB_OSTDL_PORT(10), 0x2}, {SMI_LARB_OSTDL_PORT(11), 0x2},
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{SMI_LARB_OSTDL_PORT(12), 0x4}, {SMI_LARB_OSTDL_PORT(13), 0x4},
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{SMI_LARB_OSTDL_PORT(14), 0x4}, {SMI_LARB_OSTDL_PORT(15), 0x2},
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{SMI_LARB_OSTDL_PORT(16), 0x2}, {SMI_LARB_OSTDL_PORT(17), 0x2},
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{SMI_LARB_OSTDL_PORT(18), 0x2}, {SMI_LARB_OSTDL_PORT(19), 0x2},
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{SMI_LARB_OSTDL_PORT(20), 0x2},
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};
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/* {imgo(0), 0x16}, {rrzo(1), 0x14} */
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/* scen: ALL */
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struct mtk_smi_pair *smi_comm_scen_pair[SMI_SCEN_NUM] = {
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smi_comm_init_pair, smi_comm_icfp_pair,
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};
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struct mtk_smi_pair *smi_larb0_scen_pair[SMI_SCEN_NUM] = {
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smi_larb0_init_pair, smi_larb0_icfp_pair,
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};
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struct mtk_smi_pair *smi_larb1_scen_pair[SMI_SCEN_NUM] = {
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smi_larb1_init_pair, smi_larb1_init_pair,
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};
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struct mtk_smi_pair *smi_larb2_scen_pair[SMI_SCEN_NUM] = {
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smi_larb2_init_pair, smi_larb2_icfp_pair,
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};
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struct mtk_smi_pair *smi_larb3_scen_pair[SMI_SCEN_NUM] = {
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smi_larb3_init_pair, smi_larb3_icfp_pair,
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};
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u32 smi_scen_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_PORT_NUM, SMI_LARB1_PORT_NUM,
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SMI_LARB2_PORT_NUM, SMI_LARB3_PORT_NUM,
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SMI_LARB_NUM,
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};
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struct mtk_smi_pair **smi_scen_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_scen_pair, smi_larb1_scen_pair,
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smi_larb2_scen_pair, smi_larb3_scen_pair,
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smi_comm_scen_pair,
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};
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#endif
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