threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
203 lines
6.0 KiB
C
203 lines
6.0 KiB
C
/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#include <linux/delay.h>
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#include <mt-plat/upmu_common.h>
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#include <mt-plat/mtk_chip.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include "include/pmic.h"
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#include "include/pmic_api.h"
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#include "include/pmic_api_buck.h"
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#define LP_INIT_SETTING_VERIFIED 1
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unsigned int g_pmic_chip_version = 1;
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int PMIC_MD_INIT_SETTING_V1(void)
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{
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/* No need for PMIC MT6359 */
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return 0;
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}
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int PMIC_check_wdt_status(void)
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{
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unsigned int ret = 0;
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is_wdt_reboot_pmic = pmic_get_register_value(PMIC_WDTRSTB_STATUS);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_SET, 0x8);
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udelay(50);
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is_wdt_reboot_pmic_chk = pmic_get_register_value(PMIC_WDTRSTB_STATUS);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_CLR, 0x8);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_SET, 0x1);
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ret = pmic_get_register_value(PMIC_RG_WDTRSTB_EN);
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return ret;
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}
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int PMIC_check_pwrhold_status(void)
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{
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unsigned int val = 0;
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pmic_read_interface(PMIC_RG_PWRHOLD_ADDR, &val,
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PMIC_RG_PWRHOLD_MASK,
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PMIC_RG_PWRHOLD_SHIFT);
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return val;
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}
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int PMIC_check_battery(void)
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{
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unsigned int val = 0;
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/* ask shin-shyu programming guide */
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pmic_set_register_value(PMIC_RG_BATON_EN, 1);
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/*PMIC_upmu_set_baton_tdet_en(1);*/
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val = pmic_get_register_value(PMIC_AD_BATON_UNDET);
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if (val == 0) {
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pr_debug("bat is exist.\n");
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is_battery_remove = 0;
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return 1;
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}
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pr_debug("bat NOT exist.\n");
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is_battery_remove = 1;
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return 0;
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}
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int PMIC_POWER_HOLD(unsigned int hold)
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{
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if (hold > 1) {
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pr_notice("[%s] hold = %d only 0 or 1\n", __func__, hold);
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return -1;
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}
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if (hold)
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PMICLOG("[%s] ON\n", __func__);
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else
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PMICLOG("[%s] OFF\n", __func__);
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pmic_config_interface_nolock(PMIC_RG_PWRHOLD_ADDR, hold,
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PMIC_RG_PWRHOLD_MASK,
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PMIC_RG_PWRHOLD_SHIFT);
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PMICLOG("[PMIC_KERNEL] PowerHold = 0x%x\n"
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, pmic_get_register_value(PMIC_RG_PWRHOLD));
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return 0;
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}
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unsigned int PMIC_CHIP_VER(void)
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{
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unsigned int ret = 0;
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unsigned short chip_ver = 0;
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chip_ver = pmic_get_register_value(PMIC_SWCID);
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ret = ((chip_ver & 0x00F0) >> 4);
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return ret;
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}
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void PMIC_LP_INIT_SETTING(void)
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{
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g_pmic_chip_version = PMIC_CHIP_VER();
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#if LP_INIT_SETTING_VERIFIED
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/*Suspend*/
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pmic_buck_vcore_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_buck_vpu_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vproc1_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vproc2_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vgpu11_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vgpu12_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vmodem_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_buck_vs2_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_proc1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_proc2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_others_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_vsram_md_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vcamio_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vm18_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vcn18_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vcn13_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, 1, HW_OFF);
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pmic_ldo_vio18_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vefuse_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrf12_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrfck_lp(SRCLKEN14, 1, 1, HW_OFF);
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pmic_ldo_va12_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_va09_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_vbbck_lp(SRCLKEN14, 1, 1, HW_OFF);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, 1, HW_OFF);
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pmic_ldo_vbif28_lp(SRCLKEN0, 1, 1, HW_OFF);
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pmic_ldo_vaud18_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vaux18_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_vxo22_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_vcn33_1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vcn33_2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vusb_lp(SRCLKEN0, 1, 1, HW_LP);
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pmic_ldo_vemc_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vio28_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vsim1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vufs_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vibr_lp(SW, 1, 1, SW_OFF);
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/*Deepidle*/
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pmic_buck_vcore_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_buck_vpu_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vproc1_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vproc2_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vgpu11_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vgpu12_lp(SW, 1, 1, SW_OFF);
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pmic_buck_vmodem_lp(SW, 1, 1, SW_ON);
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pmic_buck_vs1_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_buck_vs2_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_proc1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_proc2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsram_others_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_ldo_vsram_md_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vcamio_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vm18_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vcn18_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vcn13_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, 1, HW_OFF);
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pmic_ldo_vio18_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vefuse_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrf12_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vrfck_lp(SRCLKEN14, 1, 1, HW_OFF);
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pmic_ldo_va12_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_ldo_va09_lp(SRCLKEN2, 1, 1, HW_LP);
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/* SRCLKEN14 HW_ON no need to setting */
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/*pmic_ldo_vbbck_lp(SRCLKEN14, 1, 1, HW_ON);*/
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, 1, HW_OFF);
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pmic_ldo_vbif28_lp(SRCLKEN2, 1, 1, HW_OFF);
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pmic_ldo_vaud18_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vaux18_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_ldo_vxo22_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_ldo_vcn33_1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vcn33_2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vusb_lp(SRCLKEN2, 1, 1, HW_LP);
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pmic_ldo_vemc_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vio28_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vsim1_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, 1, SW_OFF);
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pmic_ldo_vufs_lp(SW, 1, 1, SW_ON);
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pmic_ldo_vibr_lp(SW, 1, 1, SW_OFF);
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pr_info("[%s] Chip Ver = %d\n", __func__, g_pmic_chip_version);
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#endif /*LP_INIT_SETTING_VERIFIED*/
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}
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