threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <mt-plat/upmu_common.h>
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static DEFINE_MUTEX(pmic_efuse_lock_mutex);
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unsigned int pmic_read_efuse_nolock(int i)
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{
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unsigned int efuse_data = 0;
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/* 1. enable efuse ctrl engine clock */
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pmic_set_register_value(PMIC_TOP_CKHWEN_CON0_CLR
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, 1 << PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT);
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pmic_set_register_value(PMIC_TOP_CKPDN_CON0_CLR
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, 1 << PMIC_RG_EFUSE_CK_PDN_SHIFT);
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/* 2. */
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pmic_set_register_value(PMIC_RG_OTP_RD_SW, 1);
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/* 3. Set row to read */
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pmic_set_register_value(PMIC_RG_OTP_PA, i * 2);
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/* 4. Toggle RG_OTP_RD_TRIG */
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if (pmic_get_register_value(PMIC_RG_OTP_RD_TRIG) == 0)
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pmic_set_register_value(PMIC_RG_OTP_RD_TRIG, 1);
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else
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pmic_set_register_value(PMIC_RG_OTP_RD_TRIG, 0);
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/* 5. Polling RG_OTP_RD_BUSY = 0 */
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udelay(300);
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while (pmic_get_register_value(PMIC_RG_OTP_RD_BUSY) == 1)
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;
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/* 6. Read RG_OTP_DOUT_SW */
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udelay(100);
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efuse_data = pmic_get_register_value(PMIC_RG_OTP_DOUT_SW);
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/* 7. disable efuse ctrl engine clock */
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pmic_set_register_value(PMIC_TOP_CKHWEN_CON0_SET
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, 1 << PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT);
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pmic_set_register_value(PMIC_TOP_CKPDN_CON0_SET
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, 1 << PMIC_RG_EFUSE_CK_PDN_SHIFT);
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return efuse_data;
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}
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unsigned int pmic_Read_Efuse_HPOffset(int i)
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{
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unsigned int efuse_data = 0;
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mutex_lock(&pmic_efuse_lock_mutex);
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efuse_data = pmic_read_efuse_nolock(i);
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mutex_unlock(&pmic_efuse_lock_mutex);
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return efuse_data;
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}
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