threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
132 lines
3.1 KiB
C
132 lines
3.1 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pm_qos.h>
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#include <linux/delay.h>
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#include <mt-plat/mtk_otp.h>
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#include <mt-plat/upmu_common.h>
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#include <linux/regulator/consumer.h>
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#include "otp_pmic_config.h"
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#define kal_uint32 unsigned int
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static struct pm_qos_request dvfsrc_vcore_opp_req;
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static struct regulator *reg_vcore;
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static unsigned int org_volt;
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/**************************************************************************
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*EXTERN FUNCTION
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**************************************************************************/
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u32 otp_pmic_fsource_set(void)
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{
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u32 ret_val = 0;
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/* 1.8V */
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ret_val |= pmic_config_interface(
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(kal_uint32)(PMIC_RG_VEFUSE_VOSEL_ADDR),
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(kal_uint32)(0xC),
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(kal_uint32)(PMIC_RG_VEFUSE_VOSEL_MASK),
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(kal_uint32)(PMIC_RG_VEFUSE_VOSEL_SHIFT)
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);
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/* +0mV */
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ret_val |= pmic_config_interface(
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(kal_uint32)(PMIC_RG_VEFUSE_VOCAL_ADDR),
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(kal_uint32)(0x0),
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(kal_uint32)(PMIC_RG_VEFUSE_VOCAL_MASK),
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(kal_uint32)(PMIC_RG_VEFUSE_VOCAL_SHIFT)
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);
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/* Fsource(VEFUSE) enabled */
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ret_val |= pmic_config_interface(
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_ADDR),
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(kal_uint32)(1),
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_MASK),
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_SHIFT));
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mdelay(10);
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return ret_val;
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}
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u32 otp_pmic_fsource_release(void)
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{
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u32 ret_val = 0;
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/* Fsource(VEFUSE) disabled */
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ret_val |= pmic_config_interface(
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_ADDR),
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(kal_uint32)(0),
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_MASK),
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_SHIFT));
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mdelay(10);
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return ret_val;
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}
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u32 otp_pmic_is_fsource_enabled(void)
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{
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u32 regVal = 0;
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/* Check Fsource(VEFUSE) Status */
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pmic_read_interface((kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_ADDR),
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®Val,
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_MASK),
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(kal_uint32)(PMIC_RG_LDO_VEFUSE_EN_SHIFT)
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);
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/* return 1 : fsource enabled
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* return 0 : fsource disabled
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*/
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return regVal;
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}
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u32 otp_pmic_high_vcore_init(void)
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{
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reg_vcore = regulator_get(NULL, "vcore");
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pm_qos_add_request(&dvfsrc_vcore_opp_req, PM_QOS_VCORE_OPP,
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PM_QOS_VCORE_OPP_DEFAULT_VALUE);
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return 0;
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}
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u32 otp_pmic_high_vcore_set(void)
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{
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/* opp 0 -> 0.725V */
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pm_qos_update_request(&dvfsrc_vcore_opp_req, 0);
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/* to 0.75V and save vcore */
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if (reg_vcore) {
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org_volt = regulator_get_voltage(reg_vcore);
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regulator_set_voltage(reg_vcore, 750000,
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750000);
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}
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return STATUS_DONE;
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}
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u32 otp_pmic_high_vcore_release(void)
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{
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/* restore vcore */
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if (reg_vcore) {
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regulator_set_voltage(reg_vcore, org_volt,
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org_volt);
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}
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pm_qos_update_request(&dvfsrc_vcore_opp_req,
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PM_QOS_VCORE_OPP_DEFAULT_VALUE);
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return STATUS_DONE;
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}
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