threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
129 lines
2.9 KiB
C
129 lines
2.9 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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* Licensed under either
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* BSD Licence, (see NOTICE for more details)
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* GNU General Public License, version 2.0, (see NOTICE for more details)
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*/
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#ifndef __NANDX_INFO_H__
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#define __NANDX_INFO_H__
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#include "nandx_util.h"
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/* The minimum oob required by user. */
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#define MIN_OOB_REQUIRED (32)
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enum OPS_MODE_TYPE {
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/* if true slc mode, else normal mode */
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OPS_MODE_SLC,
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/* if true ddr interface, else legacy mode */
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OPS_MODE_DDR,
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/* if true dma mode, else mcu mode */
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OPS_MODE_DMA,
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/* if true irq mode, else polling mode */
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OPS_MODE_IRQ,
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/* if true use ecc, else non-ecc operation */
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OPS_MODE_ECC,
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/* if true open randomizer, else close randomizer */
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OPS_MODE_RANDOMIZE,
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/* if true use calibration for error handle, else none */
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OPS_MODE_CALIBRATION,
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/* if true multi-plane, else non-multi-plane operation */
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OPS_MODE_MULTI_PLANE,
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/* if true use cache, else non-cache mode */
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OPS_MODE_CACHE,
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};
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enum OPS_MODE_MASK {
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MODE_SLC = (1 << OPS_MODE_SLC),
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MODE_DDR = (1 << OPS_MODE_DDR),
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MODE_DMA = (1 << OPS_MODE_DMA),
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MODE_IRQ = (1 << OPS_MODE_IRQ),
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MODE_ECC = (1 << OPS_MODE_ECC),
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MODE_RANDOMIZE = (1 << OPS_MODE_RANDOMIZE),
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MODE_CALIBRATION = (1 << OPS_MODE_CALIBRATION),
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MODE_MULTI = (1 << OPS_MODE_MULTI_PLANE),
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MODE_CACHE = (1 << OPS_MODE_CACHE),
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};
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enum IC_VER {
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NANDX_MT8127,
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NANDX_MT8163,
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NANDX_MT8167,
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NANDX_NONE,
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};
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#define MAX_NFI2X_CLK_NUM 10
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#define MAX_ECC_CLK_NUM 5
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struct nfc_frequency {
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/* The async clk freq if IP supports async freq */
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u32 freq_async;
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/* NFI 2x clk freq set */
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u32 freq_2x[MAX_NFI2X_CLK_NUM];
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void **nfi_clk_sets;
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int nfi_clk_num;
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/* The selected NFI2X clk. If use async freq, set it as -1. */
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int sel_2x_idx;
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/* ECC clk freq set */
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u32 freq_ecc[MAX_ECC_CLK_NUM];
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void **ecc_clk_sets;
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int ecc_clk_num;
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/* The selected ECC clk. If not use ECC clk, set it as -1. */
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int sel_ecc_idx;
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};
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/**
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* struct platform_data - nand platform data
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* @ver: IC version
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* @nfi_regs: nfi register base address
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* @ecc_regs: ecc register base address
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* @top_regs: [optional] top layer register for some NFC controller designs
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* @nfi_irq: nfi irq number
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* @ecc_irq: ecc irq number
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* @dev: [optional] platform device pointer
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*/
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struct nfc_resource {
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enum IC_VER ver;
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void *nfi_regs;
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void *ecc_regs;
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void *top_regs;
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u32 nfi_irq;
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u32 ecc_irq;
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void *dev;
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};
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struct platform_data {
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struct nfc_resource *res;
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struct nfc_frequency freq;
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void *clk_sets;
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};
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struct nandx_ops {
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u32 row;
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u32 col;
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u32 len;
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int status;
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void *data;
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void *oob;
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};
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struct nandx_chip_info {
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u8 plane_num; /* operation unit plane num */
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u8 wl_page_num;
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u32 block_num; /* total block num */
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u32 block_size;
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u32 slc_block_size;
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u32 page_size;
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u32 oob_size; /* fdm size */
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u32 sector_size;
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u32 ecc_strength; /* calc ecc */
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};
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bool nandx_get_mode(enum OPS_MODE_TYPE mode);
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int nandx_change_mode(enum OPS_MODE_TYPE mode, bool enable);
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#endif /* __NANDX_INFO_H__ */
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