threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
499 lines
14 KiB
C
499 lines
14 KiB
C
/*
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* MUSB OTG driver register defines
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2006 by Texas Instruments
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* Copyright (C) 2006-2007 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __MUSB_REGS_H__
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#define __MUSB_REGS_H__
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#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
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/*
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* MUSB Register bits
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*/
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/* CODA PORTING */
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/* DEVCTL */
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#define MUSB_DEVCTL_BDEVICE 0x80
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#define MUSB_DEVCTL_FSDEV 0x40
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#define MUSB_DEVCTL_LSDEV 0x20
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#define MUSB_DEVCTL_VBUS 0x18
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#define MUSB_DEVCTL_VBUS_SHIFT 3
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#define MUSB_DEVCTL_HM 0x04
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#define MUSB_DEVCTL_HR 0x02
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#define MUSB_DEVCTL_SESSION 0x01
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/* MUSB ULPI VBUSCONTROL */
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#define MUSB_ULPI_USE_EXTVBUS 0x01
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#define MUSB_ULPI_USE_EXTVBUSIND 0x02
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/* ULPI_REG_CONTROL */
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#define MUSB_ULPI_REG_REQ (1 << 0)
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#define MUSB_ULPI_REG_CMPLT (1 << 1)
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#define MUSB_ULPI_RDN_WR (1 << 2)
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/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
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#define MUSB_FIFOSZ_DPB 0x10
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/* Allocation size (8, 16, 32, ... 4096) */
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#define MUSB_FIFOSZ_SIZE 0x0f
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/* CSR0 in Peripheral mode */
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#define MUSB_CSR0_P_DATAEND 0x0008
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/* TxType/RxType */
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#define MUSB_TYPE_SPEED 0xc0
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#define MUSB_TYPE_SPEED_SHIFT 6
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#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
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#define MUSB_TYPE_PROTO_SHIFT 4
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#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
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/* CONFIGDATA */
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#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
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#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
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#define MUSB_CONFIGDATA_BIGENDIAN 0x20
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#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
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#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
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#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
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#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
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#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
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#ifndef CONFIG_BLACKFIN
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/*
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* Common USB registers
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*/
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#define MUSB_FADDR 0x00 /* 8-bit */
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#define MUSB_POWER 0x01 /* 8-bit */
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#define MUSB_INTRTX 0x02 /* 16-bit */
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#define MUSB_INTRRX 0x04
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#define MUSB_INTRTXE 0x06
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#define MUSB_INTRRXE 0x08
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#define MUSB_INTRUSB 0x0A /* 8 bit */
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#define MUSB_INTRUSBE 0x0B /* 8 bit */
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#define MUSB_FRAME 0x0C
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#define MUSB_INDEX 0x0E /* 8 bit */
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#define MUSB_TESTMODE 0x0F /* 8 bit */
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/* Get offset for a given FIFO from musb->mregs */
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#if defined(CONFIG_USB_MUSB_TUSB6010) || \
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defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
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#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
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#else
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#define MUSB_FIFO_OFFSET(epnum) (U3D_FIFO0 + ((epnum) * 0x10))
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#endif
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/*
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* Additional Control Registers
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*/
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#define MUSB_DEVCTL 0x60 /* 8 bit */
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/* These are always controlled through the INDEX register */
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#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
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#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
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#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
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#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
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/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
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#define MUSB_HWVERS 0x6C /* 8 bit */
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#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
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#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
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#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
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#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
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#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
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#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
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#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
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#define MUSB_EPINFO 0x78 /* 8 bit */
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#define MUSB_RAMINFO 0x79 /* 8 bit */
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#define MUSB_LINKINFO 0x7a /* 8 bit */
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#define MUSB_VPLEN 0x7b /* 8 bit */
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#define MUSB_HS_EOF1 0x7c /* 8 bit */
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#define MUSB_FS_EOF1 0x7d /* 8 bit */
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#define MUSB_LS_EOF1 0x7e /* 8 bit */
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/* Offsets to endpoint registers */
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#define MUSB_TXMAXP 0x00
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#define MUSB_TXCSR 0x02
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#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
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#define MUSB_RXMAXP 0x04
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#define MUSB_RXCSR 0x06
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#define MUSB_RXCOUNT 0x08
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#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
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#define MUSB_TXTYPE 0x0A
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#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
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#define MUSB_TXINTERVAL 0x0B
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#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
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#define MUSB_RXTYPE 0x0C
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#define MUSB_RXINTERVAL 0x0D
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#define MUSB_FIFOSIZE 0x0F
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#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x10 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(0x100 + (0x10*(_epnum)) + (_offset))
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#if defined(CONFIG_USB_MUSB_TUSB6010) || \
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defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
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/* TUSB6010 EP0 configuration register is special */
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#define MUSB_TUSB_OFFSET(_epnum, _offset) \
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(0x10 + _offset)
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#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
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#endif
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#define MUSB_TXCSR_MODE 0x2000
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/* "bus control"/target registers, for host side multipoint (external hubs) */
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#define MUSB_TXFUNCADDR 0x00
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#define MUSB_TXHUBADDR 0x02
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#define MUSB_TXHUBPORT 0x03
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#define MUSB_RXFUNCADDR 0x04
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#define MUSB_RXHUBADDR 0x06
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#define MUSB_RXHUBPORT 0x07
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#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
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(0x80 + (8*(_epnum)) + (_offset))
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static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
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{
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musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
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}
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static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
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{
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musb_writew(mbase, MUSB_TXFIFOADD, c_off);
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}
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static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
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{
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musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
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}
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static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
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{
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musb_writew(mbase, MUSB_RXFIFOADD, c_off);
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}
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static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
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{
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musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
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}
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static inline u8 musb_read_txfifosz(void __iomem *mbase)
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{
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return musb_readb(mbase, MUSB_TXFIFOSZ);
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}
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static inline u16 musb_read_txfifoadd(void __iomem *mbase)
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{
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return musb_readw(mbase, MUSB_TXFIFOADD);
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}
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static inline u8 musb_read_rxfifosz(void __iomem *mbase)
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{
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return musb_readb(mbase, MUSB_RXFIFOSZ);
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}
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static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
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{
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return musb_readw(mbase, MUSB_RXFIFOADD);
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}
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static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
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{
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return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
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}
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static inline u8 musb_read_configdata(void __iomem *mbase)
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{
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musb_writeb(mbase, MUSB_INDEX, 0);
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return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
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}
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static inline u16 musb_read_hwvers(void __iomem *mbase)
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{
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return musb_readw(mbase, MUSB_HWVERS);
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}
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static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
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{
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return MUSB_BUSCTL_OFFSET(i, 0) + mbase;
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}
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static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, u8 qh_addr_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
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}
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static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs, u8 qh_h_addr_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
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}
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static inline void musb_write_rxhubport(void __iomem *ep_target_regs, u8 qh_h_port_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
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}
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static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, u8 qh_addr_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR), qh_addr_reg);
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}
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static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, u8 qh_addr_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR), qh_addr_reg);
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}
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static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, u8 qh_h_port_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT), qh_h_port_reg);
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}
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static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
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}
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static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
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}
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static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
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}
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static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
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}
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static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
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}
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static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
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{
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return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
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}
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#else /* CONFIG_BLACKFIN */
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#define USB_BASE USB_FADDR
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#define USB_OFFSET(reg) (reg - USB_BASE)
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/*
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* Common USB registers
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*/
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#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
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#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
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#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
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#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
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#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
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#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
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#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
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#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE) /* 8 bit */
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#define MUSB_FRAME USB_OFFSET(USB_FRAME)
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#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
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#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE) /* 8 bit */
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/* Get offset for a given FIFO from musb->mregs */
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#define MUSB_FIFO_OFFSET(epnum) \
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(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
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/*
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* Additional Control Registers
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*/
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#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
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#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO) /* 8 bit */
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#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
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#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
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#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
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#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
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/* Offsets to endpoint registers */
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#define MUSB_TXMAXP 0x00
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#define MUSB_TXCSR 0x04
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#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
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#define MUSB_RXMAXP 0x08
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#define MUSB_RXCSR 0x0C
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#define MUSB_RXCOUNT 0x10
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#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
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#define MUSB_TXTYPE 0x14
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#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
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#define MUSB_TXINTERVAL 0x18
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#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
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#define MUSB_RXTYPE 0x1C
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#define MUSB_RXINTERVAL 0x20
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#define MUSB_TXCOUNT 0x28
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x40 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
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/* Not implemented - HW has separate Tx/Rx FIFO */
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#define MUSB_TXCSR_MODE 0x0000
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static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
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{
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}
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static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
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{
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}
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static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
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{
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}
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static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
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{
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}
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static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
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{
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}
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static inline u8 musb_read_txfifosz(void __iomem *mbase)
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{
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return 0;
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}
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static inline u16 musb_read_txfifoadd(void __iomem *mbase)
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{
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return 0;
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}
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static inline u8 musb_read_rxfifosz(void __iomem *mbase)
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{
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return 0;
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}
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static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
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{
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return 0;
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}
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static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
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{
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return 0;
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}
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static inline u8 musb_read_configdata(void __iomem *mbase)
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{
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return 0;
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}
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static inline u16 musb_read_hwvers(void __iomem *mbase)
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{
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/*
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* This register is invisible on Blackfin, actually the MUSB
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* RTL version of Blackfin is 1.9, so just harcode its value.
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*/
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return MUSB_HWVERS_1900;
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}
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static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
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{
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return NULL;
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}
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static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, u8 qh_addr_req)
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|
{
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|
}
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|
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static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs, u8 qh_h_addr_reg)
|
|
{
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|
}
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|
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static inline void musb_write_rxhubport(void __iomem *ep_target_regs, u8 qh_h_port_reg)
|
|
{
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|
}
|
|
|
|
static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, u8 qh_addr_reg)
|
|
{
|
|
}
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|
|
|
static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, u8 qh_addr_reg)
|
|
{
|
|
}
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|
|
|
static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, u8 qh_h_port_reg)
|
|
{
|
|
}
|
|
|
|
static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_BLACKFIN */
|
|
|
|
#endif /* __MUSB_REGS_H__ */
|