threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
133 lines
2.8 KiB
C
133 lines
2.8 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/string.h>
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#include "mmdvfs_plat.h"
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#include "mtk_qos_sram.h"
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#include "smi_pmqos.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "[mmdvfs][plat]" fmt
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#define MDP_START 5
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#define LARB_MDP_ID 1
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#define LARB_VENC_ID 3
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#define LARB_IMG_ID 5
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#define LARB_CAM_ID 6
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#define COMM_MDP_PORT 1
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#define COMM_VENC_PORT 3
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#define COMM_IMG_PORT 4
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#define COMM_CAM_PORT 7
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#ifdef QOS_BOUND_DETECT
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void mmdvfs_update_qos_sram(struct mm_larb_request larb_req[], u32 larb_update)
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{
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u32 bw;
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struct mm_qos_request *enum_req = NULL;
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if (larb_update & (1 << COMM_MDP_PORT)) {
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bw = larb_req[LARB_MDP_ID].total_bw_data;
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list_for_each_entry(enum_req,
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&larb_req[LARB_MDP_ID].larb_list, larb_node) {
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if (SMI_PMQOS_PORT_MASK(
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enum_req->master_id) < MDP_START) {
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bw -= get_comp_value(enum_req->bw_value,
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enum_req->comp_type, true);
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}
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}
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qos_sram_write(MM_SMI_MDP, bw);
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}
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if (larb_update & (1 << COMM_VENC_PORT)) {
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bw = larb_req[LARB_VENC_ID].total_bw_data;
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qos_sram_write(MM_SMI_VENC, bw);
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}
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if (larb_update & (1 << COMM_IMG_PORT)) {
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bw = larb_req[LARB_IMG_ID].total_bw_data;
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qos_sram_write(MM_SMI_IMG, bw);
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}
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if (larb_update & (1 << COMM_CAM_PORT)) {
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bw = larb_req[LARB_CAM_ID].total_bw_data;
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qos_sram_write(MM_SMI_CAM, bw);
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}
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}
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#endif
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static u32 log_common_port_ids;
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static u32 log_larb_ids;
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bool mmdvfs_log_larb_mmp(s32 common_port_id, s32 larb_id)
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{
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if (common_port_id >= 0)
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return (1 << common_port_id) & log_common_port_ids;
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if (larb_id >= 0)
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return (1 << larb_id) & log_larb_ids;
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return false;
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}
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/* Return port number of CCU on SMI common */
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inline u32 mmdvfs_get_ccu_smi_common_port(u32 master_id)
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{
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return 6;
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}
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s32 get_ccu_hrt_bw(struct mm_larb_request larb_req[])
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{
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struct mm_qos_request *enum_req = NULL;
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s32 bw = larb_req[SMI_PMQOS_LARB_DEC(get_virtual_port(
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VIRTUAL_CCU_COMMON))].total_hrt_data;
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list_for_each_entry(enum_req,
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&larb_req[LARB_CAM_ID].larb_list, larb_node) {
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if (enum_req->master_id == SMI_CCUI
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|| enum_req->master_id == SMI_CCUO
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|| enum_req->master_id == SMI_CCUG)
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bw += enum_req->hrt_value;
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}
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return bw;
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}
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s32 get_md_hrt_bw(void)
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{
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return 1600;
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}
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s32 dram_write_weight(s32 val)
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{
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return (val * 6 / 5);
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}
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s32 emi_occ_ratio(void)
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{
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return 500;
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}
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s32 emi_occ_ui_only(void)
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{
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return 500;
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}
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s32 cam_occ_ratio(void)
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{
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return 1000;
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}
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s32 disp_occ_ratio(void)
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{
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return 1000;
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}
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