threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CMDQ_DEVICE_H__
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#define __CMDQ_DEVICE_H__
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include "mdp_def.h"
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#include "mdp_common.h"
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#include <linux/clk.h>
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#define DECLARE_ENABLE_HW_CLOCK(HW_NAME) \
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u32 cmdq_dev_enable_clock_##HW_NAME(bool enable)
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DECLARE_ENABLE_HW_CLOCK(SMI_COMMON);
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DECLARE_ENABLE_HW_CLOCK(SMI_LARB0);
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#ifdef CMDQ_USE_LEGACY
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DECLARE_ENABLE_HW_CLOCK(MUTEX_32K);
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#endif
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#undef DECLARE_ENABLE_HW_CLOCK
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void cmdq_dev_get_module_clock_by_name(const char *ref_name,
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const char *clkName, struct clk **clk_module);
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u32 cmdq_dev_enable_device_clock(bool enable, struct clk *clk_module,
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const char *clkName);
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bool cmdq_dev_device_clock_is_enable(struct clk *clk_module);
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/* For test case used */
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void testcase_clkmgr_impl(enum CMDQ_ENG_ENUM engine,
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char *name, const unsigned long testWriteReg,
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const u32 testWriteValue,
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const unsigned long testReadReg, const bool verifyWriteResult);
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struct device *cmdq_dev_get(void);
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/* interrupt index */
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u32 cmdq_dev_get_irq_id(void);
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u32 cmdq_dev_get_irq_secure_id(void);
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/* GCE clock */
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void cmdq_dev_enable_gce_clock(bool enable);
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bool cmdq_dev_gce_clock_is_enable(void);
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bool cmdq_dev_mmsys_clock_is_enable(void);
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/* virtual address */
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long cmdq_dev_get_module_base_VA_GCE(void);
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unsigned long cmdq_dev_alloc_reference_VA_by_name(const char *ref_name);
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unsigned long cmdq_dev_alloc_reference_by_name(const char *ref_name,
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uint32_t *pa);
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/* Other modules information */
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void cmdq_dev_free_module_base_VA(const long VA);
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u32 cmdq_dev_get_mmsys_dummy_reg_offset(void);
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/* physical address */
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phys_addr_t cmdq_dev_get_reference_PA(const char *ref_name, int index);
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phys_addr_t cmdq_dev_get_module_base_PA_GCE(void);
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#if IS_ENABLED(CONFIG_MACH_MT6885)
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unsigned long cmdq_dev_get_va2(void);
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phys_addr_t cmdq_dev_get_pa2(void);
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#endif
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/* GCE event */
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void cmdq_dev_init_event_table(struct device_node *node);
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void cmdq_dev_test_dts_correctness(void);
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/* device initialization / deinitialization */
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void cmdq_dev_init(struct platform_device *pDevice);
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void cmdq_dev_deinit(void);
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/* dma_set_mask result, to show in status */
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s32 cmdq_dev_get_dma_mask_result(void);
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u32 cmdq_dev_get_thread_count(void);
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/* callback when read resource from device tree */
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typedef void(*CMDQ_DEV_INIT_RESOURCE_CB) (u32 engineFlag,
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enum cmdq_event resourceEvent);
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void cmdq_dev_init_resource(CMDQ_DEV_INIT_RESOURCE_CB init_cb);
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#endif /* __CMDQ_DEVICE_H__ */
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