threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
411 lines
11 KiB
C
411 lines
11 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#include <linux/jiffies.h>
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#include "mtk_ir_common.h"
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#include "mtk_ir_core.h"
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#include "mtk_ir_regs.h"
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#include "mtk_ir_cus_rcmm.h"
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#define MTK_RCMM_BITCNT_NORMAL (17)
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#define RCMM_INFO_TO_BITCNT(u4Info) \
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((u4Info & IRRX_CH_BITCNT_MASK) >> IRRX_CH_BITCNT_BITSFT)
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#define RCMM_INFO_TO_1STPULSE(u4Info) \
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((u4Info & IRRX_CH_1ST_PULSE_MASK) >> IRRX_CH_1ST_PULSE_BITSFT)
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#define RCMM_INFO_TO_2NDPULSE(u4Info) \
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((u4Info & IRRX_CH_2ND_PULSE_MASK) >> IRRX_CH_2ND_PULSE_BITSFT)
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#define RCMM_INFO_TO_3RDPULSE(u4Info) \
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((u4Info & IRRX_CH_3RD_PULSE_MASK) >> IRRX_CH_3RD_PULSE_BITSFT)
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#define IR_RCMM_DEBUG 1
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#define IR_RCMM_TAG "[IRRX_RCMM] "
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#define IR_RCMM_FUN(f) \
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do { \
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if (ir_log_debug_on) \
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pr_err(IR_RCMM_TAG"%s++++\n", __func__); \
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else \
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pr_debug(IR_RCMM_TAG"%s++++\n", __func__); \
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} while (0)
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#define IR_RCMM_LOG(fmt, args...) \
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do { \
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if (ir_log_debug_on) \
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pr_err(IR_RCMM_TAG fmt, ##args); \
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else if (IR_RCMM_DEBUG) \
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pr_debug(IR_RCMM_TAG fmt, ##args); \
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} while (0)
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#define IR_RCMM_ERR(fmt, args...) \
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pr_err(MTK_IR_TAG"%s %d : "fmt, __func__, __LINE__, ##args)
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static int mtk_ir_rcmm_enable_hwirq(int enable);
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static int mtk_ir_rcmm_init_hw(void);
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static int mtk_ir_rcmm_uninit_hw(void);
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static u32 mtk_ir_rcmm_decode(void *preserve);
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struct mtk_ir_hw ir_rcmm_cust;
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static struct mtk_ir_hw *hw = &ir_rcmm_cust;
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static u32 _u4Routine_count;
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static u32 _u4PrevKey = BTN_NONE;
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static u32 _u4Rcmm_customer_code = MTK_IR_RCMM_CUSTOMER_CODE;
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#define RCMM_REPEAT_MS 200
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#define RCMM_REPEAT_MS_MIN 60
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static struct rc_map_list mtk_rcmm_map = {
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.map = {
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.scan = mtk_rcmm_table,
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.size = ARRAY_SIZE(mtk_rcmm_table),
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.rc_proto = RC_PROTO_RCMM,
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.name = RC_MAP_MTK_RCMM,
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}
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};
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static u32 mtk_ir_rcmm_get_customer_code(void)
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{
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return _u4Rcmm_customer_code;
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}
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static u32 mtk_ir_rcmm_set_customer_code(u32 data)
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{
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_u4Rcmm_customer_code = data;
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IR_RCMM_LOG("_u4Rcmm_customer_code = 0x%x\n", _u4Rcmm_customer_code);
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return 0;
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}
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#ifdef CONFIG_HAS_EARLYSUSPEND
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static void mtk_ir_rcmm_early_suspend(void *preserve)
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{
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IR_RCMM_FUN();
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}
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static void mtk_ir_rcmm_late_resume(void *preserve)
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{
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IR_RCMM_FUN();
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}
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#else
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#define mtk_ir_rcmm_early_suspend NULL
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#define mtk_ir_rcmm_late_resume NULL
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#endif
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#ifdef CONFIG_PM_SLEEP
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static int mtk_ir_rcmm_suspend(void *preserve)
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{
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IR_RCMM_FUN();
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/* 0x24 bit[7:0]: set except register
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* 0000,0001: IRL0 & IRM0
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* 0000,0010: IRL1 & IRM1
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* 0000,0100: IRL2 & IRM2
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* 0000,1000: IRL3 & IRM3
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* 0001,0000: IRL4 & IRM4
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* 0010,0000: IRL5 & IRM5
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* 0100,0000: IRL6 & IRM6
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* 1000,0000: IRL7 & IRM7
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*/
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IR_WRITE_MASK(IRRX_WAKECLR, IRRX_WAKECLR_MASK,
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IRRX_WAKECLR_OFFSET, 0x1);
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IR_WRITE_MASK(IRRX_WAKEEN, IRRX_WAKEEN_MASK,
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IRRX_WAKEEN_OFFSET, 0x1);
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IR_WRITE_MASK(IRRX_IREXPEN, IRRX_IREXPEN_MASK,
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IRRX_IREXPEN_OFFSET, 0x1);
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IR_WRITE_MASK(IRRX_IREXPEN, IRRX_BCEPEN_MASK,
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IRRX_BCEPEN_OFFSET, 0x1);
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IR_WRITE_MASK(IRRX_EXPBCNT, IRRX_EXP_BITCNT_MASK,
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IRRX_EXP_BITCNT_OFFSET, 0x11);
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#ifdef USE_OLD_IRRX_CODA
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IR_WRITE_MASK(IRRX_PDWNOUT, IRRX_PDWNOUT_MASK,
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IRRX_PDWNOUT_OFFSET, 0x1);
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#endif
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IR_WRITE32(IRRX_ENEXP_IRM, MTK_RCMM_EXP_IRM_BIT_MASK);
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IR_WRITE32(IRRX_ENEXP_IRL, MTK_RCMM_EXP_IRL_BIT_MASK);
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IR_WRITE32(IRRX_EXP_IRM0, MTK_RCMM_EXP_POWE_KEY1);
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IR_WRITE32(IRRX_EXP_IRL0, MTK_RCMM_EXP_POWE_KEY2);
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return 0;
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}
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static int mtk_ir_rcmm_resume(void *preserve)
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{
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IR_RCMM_FUN();
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IR_WRITE_MASK(IRRX_IREXPEN, IRRX_IREXPEN_MASK,
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IRRX_IREXPEN_OFFSET, 0x0);
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IR_WRITE_MASK(IRRX_IREXPEN, IRRX_BCEPEN_MASK,
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IRRX_BCEPEN_OFFSET, 0x0);
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IR_WRITE_MASK(IRRX_WAKEEN, IRRX_WAKEEN_MASK,
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IRRX_WAKEEN_OFFSET, 0x0);
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#ifdef USE_OLD_IRRX_CODA
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IR_WRITE_MASK(IRRX_PDWNOUT, IRRX_PDWNOUT_MASK,
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IRRX_PDWNOUT_OFFSET, 0x0);
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#endif
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IR_WRITE_MASK(IRRX_WAKECLR, IRRX_WAKECLR_MASK,
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IRRX_WAKECLR_OFFSET, 0x1);
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return 0;
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}
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#else
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#define mtk_ir_rcmm_suspend NULL
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#define mtk_ir_rcmm_resume NULL
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#endif
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static int mtk_ir_rcmm_enable_hwirq(int enable)
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{
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IR_RCMM_LOG("IRRX enable hwirq: %d\n", enable);
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if (enable) {
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IR_WRITE_MASK(IRRX_IRINT_CLR, IRRX_INTCLR_MASK,
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IRRX_INTCLR_OFFSET, 0x1);
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dsb(sy);
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IR_WRITE_MASK(IRRX_IRCLR, IRRX_IRCLR_MASK,
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IRRX_IRCLR_OFFSET, 0x1);
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dsb(sy);
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IR_WRITE_MASK(IRRX_IRINT_EN, IRRX_INTEN_MASK,
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IRRX_INTEN_OFFSET, 0x1);
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dsb(sy);
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} else {
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IR_WRITE_MASK(IRRX_IRINT_CLR, IRRX_INTCLR_MASK,
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IRRX_INTCLR_OFFSET, 0x1);
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dsb(sy);
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IR_WRITE_MASK(IRRX_IRINT_EN, IRRX_INTEN_MASK,
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IRRX_INTEN_OFFSET, 0x0);
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dsb(sy);
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}
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return 0;
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}
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/*
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* This timer function is for RCMM routine work.
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* You can add stuff you want to do in this function.
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*/
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static int mtk_ir_rcmm_timer_func(const char *data)
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{
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u32 CHK_CNT_PULSE = 0;
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CHK_CNT_PULSE = (IR_READ32(IRRX_EXPBCNT) >> IRRX_IRCHK_CNT_OFFSET) &
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IRRX_IRCHK_CNT;
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if (CHK_CNT_PULSE == IRRX_IRCHK_CNT) {
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_u4Routine_count++;
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if (data[0]) {
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IR_RCMM_ERR("CHK_CNT_PULSE = 0x%x\n", CHK_CNT_PULSE);
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IR_RCMM_ERR("_u4Routine_count=%d\n", _u4Routine_count);
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}
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return mtk_ir_rcmm_enable_hwirq(1);
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}
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return 0;
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}
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static struct mtk_ir_core_platform_data mtk_ir_pdata_rcmm = {
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.device_name = MTK_INPUT_DEVICE_NAME,
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.p_map_list = &mtk_rcmm_map,
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.i4_keypress_timeout = MTK_IR_RCMM_KEYPRESS_TIMEOUT,
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.enable_hwirq = mtk_ir_rcmm_enable_hwirq,
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.init_hw = mtk_ir_rcmm_init_hw,
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.uninit_hw = mtk_ir_rcmm_uninit_hw,
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.ir_hw_decode = mtk_ir_rcmm_decode,
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.get_customer_code = mtk_ir_rcmm_get_customer_code,
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.set_customer_code = mtk_ir_rcmm_set_customer_code,
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.timer_func = mtk_ir_rcmm_timer_func,
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.mouse_step = {
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MOUSE_SMALL_X_STEP,
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MOUSE_SMALL_Y_STEP,
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MOUSE_LARGE_X_STEP,
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MOUSE_LARGE_Y_STEP
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},
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#ifdef CONFIG_HAS_EARLYSUSPEND
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.early_suspend = mtk_ir_rcmm_early_suspend,
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.late_resume = mtk_ir_rcmm_late_resume,
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#endif
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#ifdef CONFIG_PM_SLEEP
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.suspend = mtk_ir_rcmm_suspend,
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.resume = mtk_ir_rcmm_resume,
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#endif
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};
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static int mtk_ir_rcmm_uninit_hw(void)
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{
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mtk_ir_rcmm_enable_hwirq(0);
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rc_map_unregister(&mtk_rcmm_map);
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return 0;
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}
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static int mtk_ir_rcmm_init_hw(void)
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{
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enum MTK_IR_MODE ir_mode = mtk_ir_core_getmode();
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struct rc_map_table *p_table = NULL;
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int size = 0;
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int i = 0;
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IR_RCMM_FUN();
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IR_RCMM_LOG(" ir_mode = %d\n", ir_mode);
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if (ir_mode == MTK_IR_FACTORY) {
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mtk_rcmm_map.map.scan = mtk_rcmm_factory_table;
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mtk_rcmm_map.map.size = ARRAY_SIZE(mtk_rcmm_factory_table);
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} else {
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mtk_rcmm_map.map.scan = mtk_rcmm_table;
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mtk_rcmm_map.map.size = ARRAY_SIZE(mtk_rcmm_table);
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p_table = mtk_rcmm_map.map.scan;
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size = mtk_rcmm_map.map.size;
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memset(&(mtk_ir_pdata_rcmm.mouse_code), 0xff,
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sizeof(mtk_ir_pdata_rcmm.mouse_code));
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for (; i < size; i++) {
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if (p_table[i].keycode == KEY_LEFT)
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mtk_ir_pdata_rcmm.mouse_code.scanleft =
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p_table[i].scancode;
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else if (p_table[i].keycode == KEY_RIGHT)
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mtk_ir_pdata_rcmm.mouse_code.scanright =
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p_table[i].scancode;
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else if (p_table[i].keycode == KEY_UP)
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mtk_ir_pdata_rcmm.mouse_code.scanup =
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p_table[i].scancode;
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else if (p_table[i].keycode == KEY_DOWN)
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mtk_ir_pdata_rcmm.mouse_code.scandown =
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p_table[i].scancode;
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else if (p_table[i].keycode == KEY_ENTER)
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mtk_ir_pdata_rcmm.mouse_code.scanenter =
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p_table[i].scancode;
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}
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mtk_ir_pdata_rcmm.mouse_support = MTK_IR_SUPPORT_MOUSE_INPUT;
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mtk_ir_pdata_rcmm.mouse_code.scanswitch =
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MTK_IR_MOUSE_RCMM_SWITCH_CODE;
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mtk_ir_pdata_rcmm.mousename[0] = '\0';
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strcat(mtk_ir_pdata_rcmm.mousename,
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mtk_ir_pdata_rcmm.device_name);
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strcat(mtk_ir_pdata_rcmm.mousename, "_Mouse");
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mtk_ir_mouse_set_device_mode(MTK_IR_MOUSE_MODE_DEFAULT);
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}
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rc_map_register(&mtk_rcmm_map);
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IR_RCMM_LOG(" rc_map_register ok.\n");
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/* disable interrupt */
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mtk_ir_rcmm_enable_hwirq(0);
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IR_WRITE32(IRRX_CONFIG_HIGH_REG, MTK_RCMM_CONFIG);
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IR_WRITE32(IRRX_CONFIG_LOW_REG, MTK_RCMM_SAPERIOD);
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IR_WRITE32(IRRX_THRESHOLD_REG, MTK_RCMM_THRESHOLD);
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IR_WRITE32(IRRX_RCMM_THD_REG, MTK_RCMM_THRESHOLD_REG);
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IR_WRITE32(IRRX_RCMM_THD_REG0, MTK_RCMM_THRESHOLD_REG_0);
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IR_RCMM_LOG(" config:0x%08x %08x, threshold:0x%08x\n",
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IR_READ32(IRRX_CONFIG_HIGH_REG), IR_READ32(IRRX_CONFIG_LOW_REG),
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IR_READ32(IRRX_THRESHOLD_REG));
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IR_RCMM_LOG("rcmm_threshold_reg: 0x%08x, rcmm_threshold_reg0: 0x%08x\n",
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IR_READ32(IRRX_RCMM_THD_REG), IR_READ32(IRRX_RCMM_THD_REG0));
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IR_RCMM_LOG("%s----\n", _func__);
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return 0;
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}
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u32 mtk_ir_rcmm_decode(void *preserve)
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{
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u32 _au4IrRxData[2];
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u32 _u4Info = IR_READ32(IRRX_COUNT_HIGH_REG);
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u32 u4BitCnt = RCMM_INFO_TO_BITCNT(_u4Info);
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u32 u4GroupID = 0;
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char *pu1Data = (char *)_au4IrRxData;
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static unsigned long last_jiffers;
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unsigned long current_jiffers = jiffies;
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_au4IrRxData[0] = IR_READ32(IRRX_COUNT_MID_REG);
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_au4IrRxData[1] = IR_READ32(IRRX_COUNT_LOW_REG);
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if ((_au4IrRxData[0] != 0) ||
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(_au4IrRxData[1] != 0) ||
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(_u4Info != 0)) {
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IR_RCMM_LOG("IRRX Info:0x%08x data:0x%08x %08x\n", _u4Info,
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_au4IrRxData[1], _au4IrRxData[0]);
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} else {
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IR_RCMM_ERR("invalid key!!!\n");
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return BTN_INVALID_KEY;
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}
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/* Check invalid pulse */
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if (u4BitCnt != MTK_RCMM_BITCNT_NORMAL) {
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IR_RCMM_ERR("u4BitCnt(%d), should be(%d)!!!\n", u4BitCnt,
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MTK_RCMM_BITCNT_NORMAL);
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_u4PrevKey = BTN_NONE;
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goto end;
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}
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/* Check GroupId */
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u4GroupID = (pu1Data[0] & 0xf0);
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if (u4GroupID != _u4Rcmm_customer_code) {
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IR_RCMM_ERR("invalid customer code 0x%x!!!\n", u4GroupID);
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_u4PrevKey = BTN_NONE;
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goto end;
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}
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_u4PrevKey = MTK_IR_RCMM_GET_KEYCODE(pu1Data[3]);
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end:
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IR_RCMM_LOG("repeat_out=%dms\n", jiffies_to_msecs(current_jiffers -
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last_jiffers));
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last_jiffers = current_jiffers;
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MTK_IR_KEY_LOG("ID:0x%08x, Key:0x%08x\n", u4GroupID, _u4PrevKey);
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return _u4PrevKey;
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}
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static int ir_rcmm_local_init(void)
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{
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int err = 0;
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IR_RCMM_FUN();
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err += mtk_ir_register_ctl_data_path(&mtk_ir_pdata_rcmm, hw,
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RC_PROTO_RCMM);
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IR_RCMM_LOG("%s(%d)----\n", __func__, err);
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return err;
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}
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static int ir_rcmm_remove(void)
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{
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int err = 0;
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/* err += mtk_ir_rcmm_uninit_hw(); */
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return err;
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}
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static struct mtk_ir_init_info ir_rcmm_init_info = {
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.name = "ir_rcmm",
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.init = ir_rcmm_local_init,
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.uninit = ir_rcmm_remove,
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};
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static int __init ir_rcmm_init(void)
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{
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IR_RCMM_FUN();
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hw = get_mtk_ir_cus_dts(hw);
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if (hw == NULL)
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IR_RCMM_ERR("get dts info fail\n");
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mtk_ir_driver_add(&ir_rcmm_init_info);
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IR_RCMM_LOG("%s----\n", __func__);
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return 0;
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}
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static void __exit ir_rcmm_exit(void)
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{
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IR_RCMM_FUN();
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}
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module_init(ir_rcmm_init);
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module_exit(ir_rcmm_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("mtk ir_rcmm driver");
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MODULE_AUTHOR("Zhimin.Tang@mediatek.com");
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