threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/arm-smccc.h>
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#include <mt-plat/sync_write.h>
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#include <mt-plat/mtk_io.h>
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#include <mt-plat/mtk_secure_api.h>
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#include <devmpu.h>
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#include "mt_emi.h"
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static void __iomem *CEN_EMI_BASE;
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enum {
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MASTER_APM0 = 0,
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MASTER_APM1 = 1,
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MASTER_MM0 = 2,
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MASTER_MDMCU = 3,
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MASTER_MD = 4,
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MASTER_MM1 = 5,
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MASTER_GPU0_PERI = 6,
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MASTER_GPU1_LPDMA = 7,
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MASTER_ALL = 8
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};
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#define MDMCU_DOMAIN 1
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#define MDHW_DOMAIN 7
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int is_md_master(unsigned int master_id,
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unsigned int domain_id)
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{
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if ((domain_id != MDMCU_DOMAIN) &&
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(domain_id != MDHW_DOMAIN))
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return 0;
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if ((master_id & 0x7) == MASTER_MDMCU)
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return 1;
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if ((master_id & 0x7) == MASTER_MD)
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return 1;
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return 0;
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}
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void set_ap_region_permission(unsigned int apc[EMI_MPU_DGROUP_NUM])
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{
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SET_ACCESS_PERMISSION(apc, LOCK,
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FORBIDDEN, FORBIDDEN, SEC_RW, NO_PROTECTION,
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NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION,
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FORBIDDEN, SEC_R_NSEC_RW, NO_PROTECTION, NO_PROTECTION,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION);
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}
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void bypass_init(unsigned int *init_flag)
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{
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CEN_EMI_BASE = mt_cen_emi_base_get();
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*init_flag = 1;
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}
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static void clear_devmpu_violation(void)
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{
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unsigned int mpus, mput, mput_2nd;
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unsigned int i;
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struct arm_smccc_res smc_res;
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/* clear violation status */
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for (i = 0; i < EMI_MPU_DOMAIN_NUM; i++) {
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/* clear region abort violation */
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mt_reg_sync_writel(0xFFFFFFFF, EMI_MPUD_ST(i));
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/* clear out-of-range violation */
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mt_reg_sync_writel(0x3, EMI_MPUD_ST2(i));
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}
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/* clear debug info */
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mt_reg_sync_writel(0x80000000, EMI_MPUS);
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mpus = readl(IOMEM(EMI_MPUS));
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mput = readl(IOMEM(EMI_MPUT));
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if (mpus) {
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pr_info("[DEVMPU] fail to clear violation\n");
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pr_info("[DEVMPU] EMI_MPUS: %x, EMI_MPUT: %x\n", mpus, mput);
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}
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/* clear hyp violation status */
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arm_smccc_smc(MTK_SIP_KERNEL_DEVMPU_VIO_CLR,
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0, 0, 0, 0, 0, 0, 0, &smc_res);
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mput_2nd = readl(IOMEM(EMI_MPUT_2ND));
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if ((smc_res.a0) || ((mput_2nd >> 21) & 0x3)) {
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pr_info("[MPU] fail to clear hypervisor violation\n");
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pr_info("[MPU] EMI_MPT_2ND: %x\n", mput_2nd);
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}
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}
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int bypass_violation(unsigned int mpus, unsigned int *init_flag)
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{
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unsigned int mput, mput_2nd;
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unsigned long long vio_addr;
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unsigned int master_id, domain_id;
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unsigned int port_id;
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unsigned int wr_vio, wr_oo_vio;
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unsigned int hp_wr_vio;
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mput = readl(IOMEM(EMI_MPUT));
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mput_2nd = readl(IOMEM(EMI_MPUT_2ND));
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vio_addr = ((((unsigned long long)(mput_2nd & 0xF)) << 32) + mput +
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DRAM_OFFSET);
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hp_wr_vio = (mput_2nd >> 21) & 0x3;
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master_id = mpus & 0xFFFF;
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domain_id = (mpus >> 21) & 0xF;
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wr_vio = (mpus >> 29) & 0x3;
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wr_oo_vio = (mpus >> 27) & 0x3;
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port_id = master_id & 0x7;
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/* if is hyperviosr MPU violation, deliver to DevMPU */
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if (hp_wr_vio) {
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devmpu_print_violation(vio_addr, master_id, domain_id,
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hp_wr_vio, true);
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clear_devmpu_violation();
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return 1;
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}
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#if defined(CONFIG_MTK_ENABLE_GENIEZONE) \
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|| defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
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if ((wr_vio == 2) && (wr_oo_vio == 0) &&
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((port_id == 0) || (port_id == 1)))
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return 1;
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#endif
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return 0;
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}
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