threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CMDQ_DRIVER_H__
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#define __CMDQ_DRIVER_H__
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#include <linux/kernel.h>
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#include "cmdq_v3_def.h"
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struct cmdqUsageInfoStruct {
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/* [OUT] current engine ref count */
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uint32_t count[CMDQ_MAX_ENGINE_COUNT];
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};
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struct cmdqJobStruct {
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struct cmdqCommandStruct command; /* [IN] the job to perform */
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cmdqJobHandle_t hJob; /* [OUT] handle to resulting job */
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};
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struct cmdqJobResultStruct {
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/* [IN] Job handle from CMDQ_IOCTL_ASYNC_JOB_EXEC */
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cmdqJobHandle_t hJob;
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uint64_t engineFlag; /* [OUT] engine flag passed down originally */
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/* [IN/OUT] read register values, if any.
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* as input, the "count" field must represent
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* buffer space pointed by "regValues".
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* Upon return, CMDQ driver fills "count" with
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* actual requested register count.
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* However, if the input "count" is too small,
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* -ENOMEM is returned, and "count" is filled
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* with requested register count.
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*/
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struct cmdqRegValueStruct regValue;
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/* [IN/OUT] physical address to read */
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struct cmdqReadAddressStruct readAddress;
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};
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struct cmdqWriteAddressStruct {
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/* [IN] count of the writable buffer
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* (unit is # of u32, NOT in byte)
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*/
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uint32_t count;
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/* [OUT] When Alloc, this is the resulting PA.
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* It is guaranteed to be continuous.
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* [IN] When Free, please pass returned address down to ioctl.
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*
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* indeed param startPA should be UNSIGNED LONG type for 64 bit kernel
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* Considering our plartform supports max 4GB RAM
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* (upper-32bit don't care for SW)
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* and consistent common code interface, remain u32 type.
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*/
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uint32_t startPA;
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};
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#define CMDQ_IOCTL_MAGIC_NUMBER 'x'
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#define CMDQ_IOCTL_LOCK_MUTEX _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 1, int)
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#define CMDQ_IOCTL_UNLOCK_MUTEX _IOR(CMDQ_IOCTL_MAGIC_NUMBER, 2, int)
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#define CMDQ_IOCTL_EXEC_COMMAND _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 3, \
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struct cmdqCommandStruct)
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#define CMDQ_IOCTL_QUERY_USAGE _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 4, \
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struct cmdqUsageInfoStruct)
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/* */
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/* Async operations */
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/* */
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#define CMDQ_IOCTL_ASYNC_JOB_EXEC _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 5, \
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struct cmdqJobStruct)
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#define CMDQ_IOCTL_ASYNC_JOB_WAIT_AND_CLOSE _IOR(CMDQ_IOCTL_MAGIC_NUMBER, 6, \
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struct cmdqJobResultStruct)
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#define CMDQ_IOCTL_ALLOC_WRITE_ADDRESS _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 7, \
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struct cmdqWriteAddressStruct)
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#define CMDQ_IOCTL_FREE_WRITE_ADDRESS _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 8, \
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struct cmdqWriteAddressStruct)
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#define CMDQ_IOCTL_READ_ADDRESS_VALUE _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 9, \
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struct cmdqReadAddressStruct)
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/* */
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/* Chip capability query. output parameter is a bit field. */
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/* Bit definition is CMDQ_CAP_BITS. */
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/* */
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#define CMDQ_IOCTL_QUERY_CAP_BITS _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 10, int)
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/* */
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/* HW info. from DTS */
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/* */
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#define CMDQ_IOCTL_QUERY_DTS _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 11, \
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struct cmdqDTSDataStruct)
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/* */
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/* Notify MDP will use specified engine before really use. */
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/* input int is same as EngineFlag. */
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/* */
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#define CMDQ_IOCTL_NOTIFY_ENGINE _IOW(CMDQ_IOCTL_MAGIC_NUMBER, 12, uint64_t)
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#endif /* __CMDQ_DRIVER_H__ */
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