threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
124 lines
4.3 KiB
C
124 lines
4.3 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __HAL_BTIF_H_
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#define __HAL_BTIF_H_
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#ifndef CONFIG_OF
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#define MTK_BTIF_REG_BASE BTIF_BASE
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#endif
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#if defined(CONFIG_MTK_CLKMGR)
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#if defined(CONFIG_ARCH_MT6580)
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#define MTK_BTIF_CG_BIT MT_CG_BTIF_SW_CG
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#elif defined(CONFIG_ARCH_MT6735)
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#define MTK_BTIF_CG_BIT MT_CG_PERI_BTIF
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#elif defined(CONFIG_ARCH_MT6735M)
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#define MTK_BTIF_CG_BIT MT_CG_PERI_BTIF
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#elif defined(CONFIG_ARCH_MT6753)
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#define MTK_BTIF_CG_BIT MT_CG_PERI_BTIF
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#endif
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#else
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struct clk *clk_btif_apdma; /*btif apdma clock*/
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struct clk *clk_btif; /*btif clock*/
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#endif /* !defined(CONFIG_MTK_CLKMGR) */
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#define BTIF_RBR(base) (unsigned long)(base + 0x0)
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/*RX Buffer Register: read only */
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#define BTIF_THR(base) (unsigned long)(base + 0x0)
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/*Rx Holding Register: write only */
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#define BTIF_IER(base) (unsigned long)(base + 0x4)
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/*Interrupt Enable Register: read/write */
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#define BTIF_IIR(base) (unsigned long)(base + 0x8)
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/*Interrupt Identification Register: read only */
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#define BTIF_FIFOCTRL(base) (unsigned long)(base + 0x8)
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/*FIFO Control Register: write only */
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#define BTIF_FAKELCR(base) (unsigned long)(base + 0xC)
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/*FAKE LCR Register: read/write */
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#define BTIF_LSR(base) (unsigned long)(base + 0x14)
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/*Line Status Register: read only */
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#define BTIF_SLEEP_EN(base) (unsigned long)(base + 0x48)
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/*Sleep Enable Register: read/write */
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#define BTIF_DMA_EN(base) (unsigned long)(base + 0x4C)
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/*DMA Enable Register: read/write */
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#define BTIF_RTOCNT(base) (unsigned long)(base + 0x54)
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/*Rx Timeout Count Register: read/write */
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#define BTIF_TRI_LVL(base) (unsigned long)(base + 0x60)
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/*Tx/Rx Trigger Level Control Register: read/write */
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#define BTIF_WAK(base) (unsigned long)(base + 0x64)
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/*BTIF module wakeup Register: write only */
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#define BTIF_WAT_TIME(base) (unsigned long)(base + 0x68)
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/*BTIF ASYNC Wait Time Control Register: read/write */
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#define BTIF_HANDSHAKE(base) (unsigned long)(base + 0x6C)
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/*BTIF New Handshake Control Register: read/write */
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/*BTIF_IER bits*/
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#define BTIF_IER_TXEEN (0x1 << 1) /*1: Tx holding register is empty */
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#define BTIF_IER_RXFEN (0x1 << 0) /*1: Rx buffer contains data */
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/*BTIF_IIR bits*/
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#define BTIF_IIR_NINT (0x1 << 0) /*No INT Pending */
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#define BTIF_IIR_TX_EMPTY (0x1 << 1) /*Tx Holding Register empty */
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#define BTIF_IIR_RX (0x1 << 2) /*Rx data received */
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#define BTIF_IIR_RX_TIMEOUT (0x11 << 2) /*Rx data received */
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/*BTIF_LSR bits*/
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#define BTIF_LSR_DR_BIT (0x1 << 0)
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#define BTIF_LSR_THRE_BIT (0x1 << 5)
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#define BTIF_LSR_TEMT_BIT (0x1 << 6)
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/*BTIF_FIFOCTRL bits*/
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#define BTIF_FIFOCTRL_CLR_TX (0x1 << 2) /*Clear Tx FIRO */
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#define BTIF_FIFOCTRL_CLR_RX (0x1 << 1) /*Clear Rx FIRO */
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/*BTIF_FAKELCR bits*/
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#define BTIF_FAKELCR_NORMAL_MODE 0x0
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/*BTIF_SLEEP_EN bits*/
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#define BTIF_SLEEP_EN_BIT (0x1 << 0) /*enable Sleep mode */
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#define BTIF_SLEEP_DIS_BIT (0x0) /*disable sleep mode */
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/*BTIF_DMA_EN bits*/
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#define BTIF_DMA_EN_RX (0x1 << 0) /*Enable Rx DMA */
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#define BTIF_DMA_EN_TX (0x1 << 1) /*Enable Tx DMA */
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#define BTIF_DMA_EN_AUTORST_EN (0x1 << 2)
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/*1: timeout counter will be auto reset */
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#define BTIF_DMA_EN_AUTORST_DIS (0x0 << 2)
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/* 0: after Rx timeout happens, */
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/* SW shall reset the interrupt by reading BTIF 0x4C */
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/*BTIF_TRI_LVL bits*/
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#define BTIF_TRI_LVL_TX_MASK ((0xf) << 0)
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#define BTIF_TRI_LVL_RX_MASK ((0x7) << 4)
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#define BTIF_TRI_LVL_TX(x) ((x & 0xf) << 0)
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#define BTIF_TRI_LVL_RX(x) ((x & 0x7) << 4)
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#define BTIF_TRI_LOOP_EN (0x1 << 7)
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#define BTIF_TRI_LOOP_DIS (0x0 << 7)
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/*BTIF_WAK bits*/
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#define BTIF_WAK_BIT (0x1 << 0)
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/*BTIF_HANDSHAKE bits*/
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#define BTIF_HANDSHAKE_EN_HANDSHAKE 1
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#define BTIF_HANDSHAKE_DIS_HANDSHAKE 0
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#define BTIF_TX_FIFO_SIZE 16
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#define BTIF_RX_FIFO_SIZE 8
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#define BTIF_TX_FIFO_THRE (BTIF_TX_FIFO_SIZE / 2)
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#define BTIF_RX_FIFO_THRE 0x1 /* 0x5 */
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#endif /*__HAL_BTIF_H_*/
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