threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
77 lines
2.4 KiB
C
77 lines
2.4 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MTK_ADC_HW_H
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#define _MTK_ADC_HW_H
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#ifdef CONFIG_OF
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extern void __iomem *auxadc_base;
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extern void __iomem *auxadc_apmix_base;
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extern void __iomem *auxadc_efuse_base;
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#undef AUXADC_BASE
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#undef APMIXED_BASE
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#undef EFUSEC_BASE
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#define AUXADC_BASE auxadc_base
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#define APMIXED_BASE auxadc_apmix_base
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#define EFUSEC_BASE auxadc_efuse_base
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#else
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#include <mach/mt_reg_base.h>
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#endif
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/* For calibration */
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#define EFUSE_CALI
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#define AUXADC_INDEX 106
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#define ADC_GE_A_MASK 0x000ffc00
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#define ADC_GE_A_SHIFT 10
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#define ADC_OE_A_MASK 0x000003ff
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#define ADC_OE_A_SHIFT 0
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#define ADC_CALI_EN_A_MASK 0x100000
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#define ADC_CALI_EN_A_SHIFT 20
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#define ADC_CALI_EN_A_REG (EFUSEC_BASE + 0x0198)
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#define ADC_GE_A_REG (EFUSEC_BASE + 0x0198)
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#define ADC_OE_A_REG (EFUSEC_BASE + 0x0198)
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#define ADC_CHANNEL_MAX 16
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#define MT_PDN_PERI_AUXADC MT_CG_PERI_AUXADC
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#define AUXADC_NODE "mediatek,auxadc"
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#define AUXADC_APMIX_NODE "mediatek,apmixedsys"
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#define AUXADC_CON0 (AUXADC_BASE + 0x000)
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#define AUXADC_CON1 (AUXADC_BASE + 0x004)
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#define AUXADC_CON1_SET (AUXADC_BASE + 0x008)
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#define AUXADC_CON1_CLR (AUXADC_BASE + 0x00C)
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#define AUXADC_CON2 (AUXADC_BASE + 0x010)
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#define AUXADC_DAT0 (AUXADC_BASE + 0x014)
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#define AUXADC_TP_CMD (AUXADC_BASE + 0x005c)
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#define AUXADC_TP_ADDR (AUXADC_BASE + 0x0060)
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#define AUXADC_TP_CON0 (AUXADC_BASE + 0x0064)
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#define AUXADC_TP_DATA0 (AUXADC_BASE + 0x0074)
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#define AUXADC_DET_VOLT (AUXADC_BASE + 0x084)
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#define AUXADC_DET_SEL (AUXADC_BASE + 0x088)
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#define AUXADC_DET_PERIOD (AUXADC_BASE + 0x08C)
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#define AUXADC_DET_DEBT (AUXADC_BASE + 0x090)
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/* For RTP, but hw don't support now */
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#define PAD_AUX_XP 16
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#define PAD_AUX_YM 16
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#define TP_CMD_ADDR_X 0x0005
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#define AUXADC_CON_RTP (APMIXED_BASE + 0x0404)
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/* SPM not use auxadc ,so mask it ****
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* #define AUXADC_CLOCK_BY_SPM
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*************/
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#endif /*_MTK_ADC_HW_H*/
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