threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
/*
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* Zoran ZR36016 basic configuration functions - header file
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*
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* Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at>
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*
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* $Id: zr36016.h,v 1.1.2.3 2003/01/14 21:18:07 rbultje Exp $
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*
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* ------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* ------------------------------------------------------------------------
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*/
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#ifndef ZR36016_H
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#define ZR36016_H
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/* data stored for each zoran jpeg codec chip */
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struct zr36016 {
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char name[32];
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int num;
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/* io datastructure */
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struct videocodec *codec;
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// coder status
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__u8 version;
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// actual coder setup
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int mode;
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__u16 xoff;
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__u16 yoff;
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__u16 width;
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__u16 height;
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__u16 xdec;
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__u16 ydec;
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};
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/* direct register addresses */
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#define ZR016_GOSTOP 0x00
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#define ZR016_MODE 0x01
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#define ZR016_IADDR 0x02
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#define ZR016_IDATA 0x03
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/* indirect register addresses */
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#define ZR016I_SETUP1 0x00
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#define ZR016I_SETUP2 0x01
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#define ZR016I_NAX_LO 0x02
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#define ZR016I_NAX_HI 0x03
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#define ZR016I_PAX_LO 0x04
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#define ZR016I_PAX_HI 0x05
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#define ZR016I_NAY_LO 0x06
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#define ZR016I_NAY_HI 0x07
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#define ZR016I_PAY_LO 0x08
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#define ZR016I_PAY_HI 0x09
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#define ZR016I_NOL_LO 0x0a
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#define ZR016I_NOL_HI 0x0b
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/* possible values for mode register */
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#define ZR016_RGB444_YUV444 0x00
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#define ZR016_RGB444_YUV422 0x01
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#define ZR016_RGB444_YUV411 0x02
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#define ZR016_RGB444_Y400 0x03
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#define ZR016_RGB444_RGB444 0x04
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#define ZR016_YUV444_YUV444 0x08
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#define ZR016_YUV444_YUV422 0x09
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#define ZR016_YUV444_YUV411 0x0a
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#define ZR016_YUV444_Y400 0x0b
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#define ZR016_YUV444_RGB444 0x0c
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#define ZR016_YUV422_YUV422 0x11
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#define ZR016_YUV422_YUV411 0x12
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#define ZR016_YUV422_Y400 0x13
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#define ZR016_YUV411_YUV411 0x16
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#define ZR016_YUV411_Y400 0x17
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#define ZR016_4444_4444 0x19
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#define ZR016_100_100 0x1b
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#define ZR016_RGB444 0x00
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#define ZR016_YUV444 0x20
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#define ZR016_YUV422 0x40
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#define ZR016_COMPRESSION 0x80
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#define ZR016_EXPANSION 0x80
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/* possible values for setup 1 register */
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#define ZR016_CKRT 0x80
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#define ZR016_VERT 0x40
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#define ZR016_HORZ 0x20
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#define ZR016_HRFL 0x10
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#define ZR016_DSFL 0x08
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#define ZR016_SBFL 0x04
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#define ZR016_RSTR 0x02
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#define ZR016_CNTI 0x01
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/* possible values for setup 2 register */
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#define ZR016_SYEN 0x40
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#define ZR016_CCIR 0x04
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#define ZR016_SIGN 0x02
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#define ZR016_YMCS 0x01
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#endif /*fndef ZR36016_H */
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