threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
2.6 KiB
C
108 lines
2.6 KiB
C
/*
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* drivers/media/i2c/smiapp-pll.h
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*
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* Generic driver for SMIA/SMIA++ compliant camera modules
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*
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* Copyright (C) 2012 Nokia Corporation
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* Contact: Sakari Ailus <sakari.ailus@iki.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef SMIAPP_PLL_H
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#define SMIAPP_PLL_H
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/* CSI-2 or CCP-2 */
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#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
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#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
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/* op pix clock is for all lanes in total normally */
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#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
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#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
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struct smiapp_pll_branch {
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uint16_t sys_clk_div;
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uint16_t pix_clk_div;
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uint32_t sys_clk_freq_hz;
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uint32_t pix_clk_freq_hz;
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};
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struct smiapp_pll {
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/* input values */
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uint8_t bus_type;
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union {
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struct {
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uint8_t lanes;
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} csi2;
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struct {
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uint8_t bus_width;
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} parallel;
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};
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unsigned long flags;
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uint8_t binning_horizontal;
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uint8_t binning_vertical;
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uint8_t scale_m;
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uint8_t scale_n;
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uint8_t bits_per_pixel;
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uint32_t link_freq;
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uint32_t ext_clk_freq_hz;
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/* output values */
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uint16_t pre_pll_clk_div;
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uint16_t pll_multiplier;
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uint32_t pll_ip_clk_freq_hz;
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uint32_t pll_op_clk_freq_hz;
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struct smiapp_pll_branch vt;
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struct smiapp_pll_branch op;
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uint32_t pixel_rate_csi;
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uint32_t pixel_rate_pixel_array;
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};
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struct smiapp_pll_branch_limits {
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uint16_t min_sys_clk_div;
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uint16_t max_sys_clk_div;
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uint32_t min_sys_clk_freq_hz;
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uint32_t max_sys_clk_freq_hz;
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uint16_t min_pix_clk_div;
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uint16_t max_pix_clk_div;
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uint32_t min_pix_clk_freq_hz;
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uint32_t max_pix_clk_freq_hz;
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};
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struct smiapp_pll_limits {
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/* Strict PLL limits */
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uint32_t min_ext_clk_freq_hz;
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uint32_t max_ext_clk_freq_hz;
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uint16_t min_pre_pll_clk_div;
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uint16_t max_pre_pll_clk_div;
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uint32_t min_pll_ip_freq_hz;
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uint32_t max_pll_ip_freq_hz;
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uint16_t min_pll_multiplier;
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uint16_t max_pll_multiplier;
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uint32_t min_pll_op_freq_hz;
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uint32_t max_pll_op_freq_hz;
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struct smiapp_pll_branch_limits vt;
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struct smiapp_pll_branch_limits op;
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/* Other relevant limits */
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uint32_t min_line_length_pck_bin;
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uint32_t min_line_length_pck;
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};
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struct device;
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int smiapp_pll_calculate(struct device *dev,
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const struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll);
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#endif /* SMIAPP_PLL_H */
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