threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "pll.h"
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include <subdev/devinit/nv04.h>
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int
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nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
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int clk, struct nvkm_pll_vals *pv)
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{
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int N1, M1, N2, M2, P;
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int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
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if (ret) {
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pv->refclk = info->refclk;
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pv->N1 = N1;
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pv->M1 = M1;
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pv->N2 = N2;
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pv->M2 = M2;
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pv->log2P = P;
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}
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return ret;
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}
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int
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nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
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{
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struct nvkm_device *device = clk->subdev.device;
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struct nvkm_devinit *devinit = device->devinit;
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int cv = device->bios->version.chip;
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if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
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cv >= 0x40) {
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if (reg1 > 0x405c)
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setPLL_double_highregs(devinit, reg1, pv);
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else
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setPLL_double_lowregs(devinit, reg1, pv);
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} else
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setPLL_single(devinit, reg1, pv);
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return 0;
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}
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static const struct nvkm_clk_func
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nv04_clk = {
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.domains = {
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{ nv_clk_src_max }
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}
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};
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int
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nv04_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
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{
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int ret = nvkm_clk_new_(&nv04_clk, device, index, false, pclk);
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if (ret == 0) {
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(*pclk)->pll_calc = nv04_clk_pll_calc;
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(*pclk)->pll_prog = nv04_clk_pll_prog;
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}
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return ret;
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}
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