threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Video Input Unit */
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#ifndef __MESON_VIU_H
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#define __MESON_VIU_H
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/* OSDx_BLKx_CFG */
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#define OSD_CANVAS_SEL 16
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#define OSD_ENDIANNESS_LE BIT(15)
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#define OSD_ENDIANNESS_BE (0)
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#define OSD_BLK_MODE_422 (0x03 << 8)
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#define OSD_BLK_MODE_16 (0x04 << 8)
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#define OSD_BLK_MODE_32 (0x05 << 8)
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#define OSD_BLK_MODE_24 (0x07 << 8)
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#define OSD_OUTPUT_COLOR_RGB BIT(7)
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#define OSD_OUTPUT_COLOR_YUV (0)
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#define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
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#define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
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#define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
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#define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
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#define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
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#define OSD_INTERLACE_ENABLED BIT(1)
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#define OSD_INTERLACE_ODD BIT(0)
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#define OSD_INTERLACE_EVEN (0)
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/* OSDx_CTRL_STAT */
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#define OSD_ENABLE BIT(21)
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#define OSD_BLK0_ENABLE BIT(0)
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#define OSD_GLOBAL_ALPHA_SHIFT 12
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/* OSDx_CTRL_STAT2 */
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#define OSD_REPLACE_EN BIT(14)
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#define OSD_REPLACE_SHIFT 6
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void meson_viu_init(struct meson_drm *priv);
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#endif /* __MESON_VIU_H */
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