threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
54 lines
2.2 KiB
C
54 lines
2.2 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef FIJI_SMC_H
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#define FIJI_SMC_H
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#include "smumgr.h"
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#include "smu73.h"
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struct fiji_pt_defaults {
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uint8_t SviLoadLineEn;
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uint8_t SviLoadLineVddC;
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uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
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uint8_t TDC_MAWt;
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uint8_t TdcWaterfallCtl;
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uint8_t DTEAmbientTempBase;
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};
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int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
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int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
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int fiji_init_smc_table(struct pp_hwmgr *hwmgr);
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int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
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int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
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int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr);
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uint32_t fiji_get_offsetof(uint32_t type, uint32_t member);
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uint32_t fiji_get_mac_definition(uint32_t value);
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int fiji_process_firmware_header(struct pp_hwmgr *hwmgr);
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int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
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bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr);
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int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
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struct amd_pp_profile *request);
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int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
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#endif
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