threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
63 lines
2.8 KiB
C
63 lines
2.8 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _SMU7_POWERTUNE_H
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#define _SMU7_POWERTUNE_H
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#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000
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#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12
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#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000
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#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12
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#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000
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#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
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#define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
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#define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
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#define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
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#define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
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#define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
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#define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
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/* PowerContainment Features */
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#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
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#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
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#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
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#define ixGC_CAC_CNTL 0x0000
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#define ixDIDT_SQ_STALL_CTRL 0x0004
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#define ixDIDT_SQ_TUNING_CTRL 0x0005
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#define ixDIDT_TD_STALL_CTRL 0x0044
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#define ixDIDT_TD_TUNING_CTRL 0x0045
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#define ixDIDT_TCP_STALL_CTRL 0x0064
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#define ixDIDT_TCP_TUNING_CTRL 0x0065
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int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr);
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int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr);
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int smu7_enable_power_containment(struct pp_hwmgr *hwmgr);
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int smu7_disable_power_containment(struct pp_hwmgr *hwmgr);
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int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
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int smu7_power_control_set_level(struct pp_hwmgr *hwmgr);
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int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);
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int smu7_disable_didt_config(struct pp_hwmgr *hwmgr);
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#endif /* DGPU_POWERTUNE_H */
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