threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Renesas SuperH DMA Engine support
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*
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __DMA_SHDMA_H
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#define __DMA_SHDMA_H
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#include <linux/sh_dma.h>
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#include <linux/shdma-base.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#define SH_DMAE_MAX_CHANNELS 20
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#define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */
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struct device;
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struct sh_dmae_chan {
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struct shdma_chan shdma_chan;
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const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
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int xmit_shift; /* log_2(bytes_per_xfer) */
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void __iomem *base;
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char dev_id[32]; /* unique name per DMAC of channel */
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int pm_error;
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dma_addr_t slave_addr;
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};
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struct sh_dmae_device {
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struct shdma_dev shdma_dev;
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struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
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const struct sh_dmae_pdata *pdata;
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struct list_head node;
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void __iomem *chan_reg;
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void __iomem *dmars;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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};
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struct sh_dmae_regs {
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u32 sar; /* SAR / source address */
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u32 dar; /* DAR / destination address */
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u32 tcr; /* TCR / transfer count */
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};
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struct sh_dmae_desc {
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struct sh_dmae_regs hw;
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struct shdma_desc shdma_desc;
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};
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#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
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#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
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#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
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#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
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struct sh_dmae_device, shdma_dev.dma_dev)
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#ifdef CONFIG_SH_DMAE_R8A73A4
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extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
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#define r8a73a4_shdma_devid (&r8a73a4_dma_pdata)
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#else
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#define r8a73a4_shdma_devid NULL
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#endif
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#endif /* __DMA_SHDMA_H */
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