threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_GDSC_H__
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#define __QCOM_GDSC_H__
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#include <linux/err.h>
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#include <linux/pm_domain.h>
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struct regmap;
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struct reset_controller_dev;
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/**
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* struct gdsc - Globally Distributed Switch Controller
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* @pd: generic power domain
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* @regmap: regmap for MMIO accesses
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* @gdscr: gsdc control register
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* @gds_hw_ctrl: gds_hw_ctrl register
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* @cxcs: offsets of branch registers to toggle mem/periph bits in
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* @cxc_count: number of @cxcs
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* @pwrsts: Possible powerdomain power states
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* @en_rest_wait_val: transition delay value for receiving enr ack signal
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* @en_few_wait_val: transition delay value for receiving enf ack signal
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* @clk_dis_wait_val: transition delay value for halting clock
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* @resets: ids of resets associated with this gdsc
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* @reset_count: number of @resets
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* @rcdev: reset controller
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*/
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struct gdsc {
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struct generic_pm_domain pd;
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struct generic_pm_domain *parent;
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struct regmap *regmap;
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unsigned int gdscr;
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unsigned int gds_hw_ctrl;
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unsigned int clamp_io_ctrl;
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unsigned int *cxcs;
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unsigned int cxc_count;
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unsigned int en_rest_wait_val;
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unsigned int en_few_wait_val;
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unsigned int clk_dis_wait_val;
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const u8 pwrsts;
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/* Powerdomain allowable state bitfields */
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#define PWRSTS_OFF BIT(0)
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#define PWRSTS_RET BIT(1)
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#define PWRSTS_ON BIT(2)
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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const u8 flags;
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#define VOTABLE BIT(0)
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#define CLAMP_IO BIT(1)
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#define HW_CTRL BIT(2)
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struct reset_controller_dev *rcdev;
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unsigned int *resets;
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unsigned int reset_count;
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};
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struct gdsc_desc {
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struct device *dev;
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struct gdsc **scs;
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size_t num;
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};
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#ifdef CONFIG_QCOM_GDSC
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int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
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struct regmap *);
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void gdsc_unregister(struct gdsc_desc *desc);
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#else
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static inline int gdsc_register(struct gdsc_desc *desc,
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struct reset_controller_dev *rcdev,
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struct regmap *r)
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{
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return -ENOSYS;
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}
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static inline void gdsc_unregister(struct gdsc_desc *desc) {};
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#endif /* CONFIG_QCOM_GDSC */
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#endif /* __QCOM_GDSC_H__ */
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