threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
43 lines
964 B
C
43 lines
964 B
C
/*
|
|
* Copyright (c) 2017 BayLibre, SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __GXBB_AOCLKC_H
|
|
#define __GXBB_AOCLKC_H
|
|
|
|
/* AO Configuration Clock registers offsets */
|
|
#define AO_RTI_PWR_CNTL_REG1 0x0c
|
|
#define AO_RTI_PWR_CNTL_REG0 0x10
|
|
#define AO_RTI_GEN_CNTL_REG0 0x40
|
|
#define AO_OSCIN_CNTL 0x58
|
|
#define AO_CRT_CLK_CNTL1 0x68
|
|
#define AO_RTC_ALT_CLK_CNTL0 0x94
|
|
#define AO_RTC_ALT_CLK_CNTL1 0x98
|
|
|
|
struct aoclk_gate_regmap {
|
|
struct clk_hw hw;
|
|
unsigned bit_idx;
|
|
struct regmap *regmap;
|
|
spinlock_t *lock;
|
|
};
|
|
|
|
#define to_aoclk_gate_regmap(_hw) \
|
|
container_of(_hw, struct aoclk_gate_regmap, hw)
|
|
|
|
extern const struct clk_ops meson_aoclk_gate_regmap_ops;
|
|
|
|
struct aoclk_cec_32k {
|
|
struct clk_hw hw;
|
|
struct regmap *regmap;
|
|
spinlock_t *lock;
|
|
};
|
|
|
|
#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
|
|
|
|
extern const struct clk_ops meson_aoclk_cec_32k_ops;
|
|
|
|
#endif /* __GXBB_AOCLKC_H */
|