threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_MUX_H
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#define __DRV_CLK_MTK_MUX_H
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#include <linux/clk-provider.h>
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struct mtk_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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const char *name;
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u32 mux_ofs;
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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s8 mux_shift;
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s8 mux_width;
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s8 gate_shift;
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s8 upd_shift;
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spinlock_t *lock;
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};
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struct mtk_mux {
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int id;
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const char *name;
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const char * const *parent_names;
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unsigned int flags;
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u32 mux_ofs;
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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s8 mux_shift;
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s8 mux_width;
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s8 gate_shift;
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s8 upd_shift;
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const struct clk_ops *ops;
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s8 num_parents;
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};
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extern const struct clk_ops mtk_mux_ops;
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extern const struct clk_ops mtk_mux_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_ops;
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extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
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#define CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) { \
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.id = _id, \
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.name = _name, \
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.mux_ofs = _mux_ofs, \
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.set_ofs = _mux_set_ofs, \
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.clr_ofs = _mux_clr_ofs, \
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.upd_ofs = _upd_ofs, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = _gate, \
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.upd_shift = _upd, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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.ops = &_ops, \
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}
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#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags) \
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CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, \
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mtk_mux_gate_clr_set_upd_ops)
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#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd) \
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MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, \
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CLK_SET_RATE_PARENT)
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struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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spinlock_t *lock);
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_onecell_data *clk_data);
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#endif /* __DRV_CLK_MTK_MUX_H */
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