threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
/*
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* Copyright (c) 2020 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6833-clk.h>
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#define MT_CLKMGR_MODULE_INIT 0
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#define MT_CCF_BRINGUP 1
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#define INV_OFS -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status pwr_stat = GATE_PWR_STAT(INV_OFS, INV_OFS,
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0x00b0, BIT(15), 0);
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static const struct mtk_gate_regs impw_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPW(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impw_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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static const struct mtk_gate impw_clks[] = {
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GATE_IMPW(CLK_IMPW_AP_CLOCK_RO_I2C0, "impw_ap_i2c0",
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"i2c_pseudo"/* parent */, 0),
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GATE_IMPW(CLK_IMPW_AP_CLOCK_RO_I2C5, "impw_ap_i2c5",
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"i2c_pseudo"/* parent */, 1),
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GATE_IMPW(CLK_IMPW_AP_CLOCK_RO_I2C7, "impw_ap_i2c7",
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"i2c_pseudo"/* parent */, 2),
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};
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static int clk_mt6833_impw_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPW_NR_CLK);
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mtk_clk_register_gates(node, impw_clks, ARRAY_SIZE(impw_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_notice("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6833_impw[] = {
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{ .compatible = "mediatek,mt6833-imp_iic_wrap_w", },
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{}
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};
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#if MT_CLKMGR_MODULE_INIT
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static struct platform_driver clk_mt6833_impw_drv = {
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.probe = clk_mt6833_impw_probe,
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.driver = {
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.name = "clk-mt6833-impw",
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.of_match_table = of_match_clk_mt6833_impw,
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},
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};
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builtin_platform_driver(clk_mt6833_impw_drv);
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#else
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static struct platform_driver clk_mt6833_impw_drv = {
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.probe = clk_mt6833_impw_probe,
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.driver = {
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.name = "clk-mt6833-impw",
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.of_match_table = of_match_clk_mt6833_impw,
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},
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};
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static int __init clk_mt6833_impw_platform_init(void)
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{
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return platform_driver_register(&clk_mt6833_impw_drv);
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}
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arch_initcall(clk_mt6833_impw_platform_init);
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#endif /* MT_CLKMGR_MODULE_INIT */
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