threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* ide.h: SPARC PCI specific IDE glue.
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*
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* Copyright (C) 1997 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Adaptation from sparc64 version to sparc by Pete Zaitcev.
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*/
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#ifndef _SPARC_IDE_H
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#define _SPARC_IDE_H
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#ifdef __KERNEL__
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#include <asm/io.h>
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#ifdef CONFIG_SPARC64
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#include <asm/pgalloc.h>
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#include <asm/spitfire.h>
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#include <asm/cacheflush.h>
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#include <asm/page.h>
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#else
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#include <asm/pgtable.h>
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#include <asm/psr.h>
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#endif
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#define __ide_insl(data_reg, buffer, wcount) \
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__ide_insw(data_reg, buffer, (wcount)<<1)
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#define __ide_outsl(data_reg, buffer, wcount) \
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__ide_outsw(data_reg, buffer, (wcount)<<1)
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/* On sparc, I/O ports and MMIO registers are accessed identically. */
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#define __ide_mm_insw __ide_insw
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#define __ide_mm_insl __ide_insl
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#define __ide_mm_outsw __ide_outsw
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#define __ide_mm_outsl __ide_outsl
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static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
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{
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#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
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unsigned long end = (unsigned long)dst + (count << 1);
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#endif
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u16 *ps = dst;
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u32 *pi;
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if(((unsigned long)ps) & 0x2) {
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*ps++ = __raw_readw(port);
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count--;
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}
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pi = (u32 *)ps;
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while(count >= 2) {
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u32 w;
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w = __raw_readw(port) << 16;
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w |= __raw_readw(port);
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*pi++ = w;
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count -= 2;
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}
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ps = (u16 *)pi;
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if(count)
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*ps++ = __raw_readw(port);
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#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
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__flush_dcache_range((unsigned long)dst, end);
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#endif
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}
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static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
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{
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#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
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unsigned long end = (unsigned long)src + (count << 1);
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#endif
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const u16 *ps = src;
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const u32 *pi;
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if(((unsigned long)src) & 0x2) {
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__raw_writew(*ps++, port);
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count--;
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}
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pi = (const u32 *)ps;
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while(count >= 2) {
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u32 w;
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w = *pi++;
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__raw_writew((w >> 16), port);
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__raw_writew(w, port);
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count -= 2;
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}
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ps = (const u16 *)pi;
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if(count)
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__raw_writew(*ps, port);
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#if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
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__flush_dcache_range((unsigned long)src, end);
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* _SPARC_IDE_H */
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