threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/serial_sci.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <cpu/serial.h>
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#include <cpu/gpio.h>
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static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned short data;
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if (cflag & CRTSCTS) {
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/* enable RTS/CTS */
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 9-2; enable all scif pins but sck */
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xfc03), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 9-2 */
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xfc03), PORT_PVCR);
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}
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} else {
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 5-2; enable only tx and rx */
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xffc3), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 5-2 */
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xffc3), PORT_PVCR);
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}
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}
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}
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struct plat_sci_port_ops sh7720_sci_port_ops = {
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.init_pins = sh7720_sci_init_pins,
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};
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