threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H
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#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H
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#define MMU_NO_CONTEXT ~0UL
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#include <asm/book3s/64/tlbflush-hash.h>
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#include <asm/book3s/64/tlbflush-radix.h>
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#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
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static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_pmd_tlb_range(vma, start, end);
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return hash__flush_tlb_range(vma, start, end);
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}
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#define __HAVE_ARCH_FLUSH_HUGETLB_TLB_RANGE
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static inline void flush_hugetlb_tlb_range(struct vm_area_struct *vma,
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unsigned long start,
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unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_hugetlb_tlb_range(vma, start, end);
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return hash__flush_tlb_range(vma, start, end);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_tlb_range(vma, start, end);
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return hash__flush_tlb_range(vma, start, end);
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_tlb_kernel_range(start, end);
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return hash__flush_tlb_kernel_range(start, end);
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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if (radix_enabled())
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return radix__local_flush_tlb_mm(mm);
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return hash__local_flush_tlb_mm(mm);
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}
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static inline void local_flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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if (radix_enabled())
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return radix__local_flush_tlb_page(vma, vmaddr);
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return hash__local_flush_tlb_page(vma, vmaddr);
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}
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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if (radix_enabled())
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return radix__tlb_flush(tlb);
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return hash__tlb_flush(tlb);
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}
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#ifdef CONFIG_SMP
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (radix_enabled())
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return radix__flush_tlb_mm(mm);
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return hash__flush_tlb_mm(mm);
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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if (radix_enabled())
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return radix__flush_tlb_page(vma, vmaddr);
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return hash__flush_tlb_page(vma, vmaddr);
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}
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#else
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#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
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#define flush_tlb_page(vma, addr) local_flush_tlb_page(vma, addr)
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#endif /* CONFIG_SMP */
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/*
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* flush the page walk cache for the address
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*/
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static inline void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address)
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{
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/*
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* Flush the page table walk cache on freeing a page table. We already
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* have marked the upper/higher level page table entry none by now.
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* So it is safe to flush PWC here.
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*/
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if (!radix_enabled())
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return;
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radix__flush_tlb_pwc(tlb, address);
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}
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#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H */
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