threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/* PCI IRQ routing on the MN103E010 based ASB2305
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*
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* This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35]
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include "pci-asb2305.h"
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void __init pcibios_irq_init(void)
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{
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}
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void __init pcibios_fixup_irqs(void)
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{
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struct pci_dev *dev = NULL;
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u8 line, pin;
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for_each_pci_dev(dev) {
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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if (pin) {
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dev->irq = XIRQ1;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
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dev->irq);
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}
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
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}
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}
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void pcibios_enable_irq(struct pci_dev *dev)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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}
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