threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/*
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* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform timer support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/mach-jz4740/base.h>
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#include <asm/mach-jz4740/timer.h>
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void __iomem *jz4740_timer_base;
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EXPORT_SYMBOL_GPL(jz4740_timer_base);
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void jz4740_timer_enable_watchdog(void)
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{
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writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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}
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EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
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void jz4740_timer_disable_watchdog(void)
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{
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writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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}
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EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
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void __init jz4740_timer_init(void)
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{
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jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
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if (!jz4740_timer_base)
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panic("Failed to ioremap timer registers");
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/* Disable all timer clocks except for those used as system timers */
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writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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/* Timer irqs are unmasked by default, mask them */
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writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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}
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