threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* Joshua Henderson <joshua.henderson@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef _ASM_MACH_PIC32_H
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#define _ASM_MACH_PIC32_H
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#include <linux/io.h>
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/*
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* PIC32 register offsets for SET/CLR/INV where supported.
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*/
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#define PIC32_CLR(_reg) ((_reg) + 0x04)
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#define PIC32_SET(_reg) ((_reg) + 0x08)
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#define PIC32_INV(_reg) ((_reg) + 0x0C)
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/*
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* PIC32 Base Register Offsets
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*/
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#define PIC32_BASE_CONFIG 0x1f800000
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#define PIC32_BASE_OSC 0x1f801200
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#define PIC32_BASE_RESET 0x1f801240
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#define PIC32_BASE_PPS 0x1f801400
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#define PIC32_BASE_UART 0x1f822000
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#define PIC32_BASE_PORT 0x1f860000
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#define PIC32_BASE_DEVCFG2 0x1fc4ff44
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/*
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* Register unlock sequence required for some register access.
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*/
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void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
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#define pic32_syskey_unlock() \
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pic32_syskey_unlock_debug(__func__, __LINE__)
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#endif /* _ASM_MACH_PIC32_H */
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