threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/*
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* Register PCI controller.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/gt64120.h>
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extern struct pci_ops gt64xxx_pci0_ops;
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static struct resource cobalt_mem_resource = {
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.start = GT_DEF_PCI0_MEM0_BASE,
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.end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
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.name = "PCI memory",
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.flags = IORESOURCE_MEM,
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};
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static struct resource cobalt_io_resource = {
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.start = 0x1000,
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.end = 0xffffffUL,
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.name = "PCI I/O",
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller cobalt_pci_controller = {
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.pci_ops = >64xxx_pci0_ops,
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.mem_resource = &cobalt_mem_resource,
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.io_resource = &cobalt_io_resource,
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.io_offset = 0 - GT_DEF_PCI0_IO_BASE,
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.io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
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};
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static int __init cobalt_pci_init(void)
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{
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register_pci_controller(&cobalt_pci_controller);
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return 0;
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}
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arch_initcall(cobalt_pci_init);
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