threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_PDA_H
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#define _ASM_IA64_SN_PDA_H
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#include <linux/cache.h>
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#include <asm/percpu.h>
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/*
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* CPU-specific data structure.
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*
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* One of these structures is allocated for each cpu of a NUMA system.
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*
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* This structure provides a convenient way of keeping together
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* all SN per-cpu data structures.
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*/
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typedef struct pda_s {
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/*
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* Support for SN LEDs
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*/
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volatile short *led_address;
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u8 led_state;
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u8 hb_state; /* supports blinking heartbeat leds */
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unsigned int hb_count;
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unsigned int idle_flag;
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volatile unsigned long *bedrock_rev_id;
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volatile unsigned long *pio_write_status_addr;
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unsigned long pio_write_status_val;
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volatile unsigned long *pio_shub_war_cam_addr;
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unsigned long sn_in_service_ivecs[4];
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int sn_lb_int_war_ticks;
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int sn_last_irq;
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int sn_first_irq;
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} pda_t;
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#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
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/*
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* PDA
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* Per-cpu private data area for each cpu. The PDA is located immediately after
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* the IA64 cpu_data area. A full page is allocated for the cp_data area for each
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* cpu but only a small amout of the page is actually used. We put the SNIA PDA
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* in the same page as the cpu_data area. Note that there is a check in the setup
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* code to verify that we don't overflow the page.
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*
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* Seems like we should should cache-line align the pda so that any changes in the
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* size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
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* or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
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*/
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DECLARE_PER_CPU(struct pda_s, pda_percpu);
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#define pda (&__ia64_per_cpu_var(pda_percpu))
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#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu))
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#endif /* _ASM_IA64_SN_PDA_H */
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