threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
140 lines
3.0 KiB
C
140 lines
3.0 KiB
C
/*
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* Cache management functions for Hexagon
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <asm/hexagon_vm.h>
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#define spanlines(start, end) \
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(((end - (start & ~(LINESIZE - 1))) >> LINEBITS) + 1)
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long lines = spanlines(start, end-1);
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unsigned long i, flags;
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start &= ~(LINESIZE - 1);
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local_irq_save(flags);
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for (i = 0; i < lines; i++) {
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__asm__ __volatile__ (
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" dccleaninva(%0); "
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:
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: "r" (start)
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);
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start += LINESIZE;
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}
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local_irq_restore(flags);
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}
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long lines = spanlines(start, end-1);
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unsigned long i, flags;
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start &= ~(LINESIZE - 1);
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local_irq_save(flags);
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for (i = 0; i < lines; i++) {
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__asm__ __volatile__ (
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" dccleana(%0); "
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" icinva(%0); "
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:
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: "r" (start)
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);
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start += LINESIZE;
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}
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__asm__ __volatile__ (
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"isync"
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);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(flush_icache_range);
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void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long lines = spanlines(start, end-1);
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unsigned long i, flags;
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start &= ~(LINESIZE - 1);
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local_irq_save(flags);
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for (i = 0; i < lines; i++) {
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__asm__ __volatile__ (
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" dccleana(%0); "
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:
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: "r" (start)
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);
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start += LINESIZE;
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}
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local_irq_restore(flags);
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}
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void hexagon_inv_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long lines = spanlines(start, end-1);
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unsigned long i, flags;
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start &= ~(LINESIZE - 1);
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local_irq_save(flags);
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for (i = 0; i < lines; i++) {
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__asm__ __volatile__ (
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" dcinva(%0); "
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:
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: "r" (start)
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);
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start += LINESIZE;
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}
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local_irq_restore(flags);
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}
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/*
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* This is just really brutal and shouldn't be used anyways,
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* especially on V2. Left here just in case.
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*/
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void flush_cache_all_hexagon(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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__vmcache_ickill();
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__vmcache_dckill();
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__vmcache_l2kill();
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local_irq_restore(flags);
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mb();
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}
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, void *src, int len)
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{
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memcpy(dst, src, len);
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if (vma->vm_flags & VM_EXEC) {
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flush_icache_range((unsigned long) dst,
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(unsigned long) dst + len);
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}
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}
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