threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/*
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* arch/arm64/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#include <asm/sysreg.h>
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#define read_gicreg(r) read_sysreg_s(SYS_ ## r)
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#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
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/*
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* Low-level accessors
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*
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* These system registers are 32 bits, but we make sure that the compiler
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* sets the GP register's most significant bits to 0 with an explicit cast.
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*/
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
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isb();
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}
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static inline void gic_write_dir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_DIR_EL1);
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isb();
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}
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static inline u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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dsb(sy);
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return irqstat;
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}
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/*
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* Cavium ThunderX erratum 23154
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*
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* The gicv3 of ThunderX requires a modified version for reading the
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* IAR status to ensure data synchronization (access to icc_iar1_el1
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* is not sync'ed before and after).
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*/
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static inline u64 gic_read_iar_cavium_thunderx(void)
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{
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u64 irqstat;
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nops(8);
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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nops(4);
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mb();
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return irqstat;
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}
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_PMR_EL1);
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_CTLR_EL1);
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isb();
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg_s(SYS_ICC_SRE_EL1);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_SRE_EL1);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_BPR1_EL1);
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}
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#define gic_read_typer(c) readq_relaxed(c)
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#define gic_write_irouter(v, c) writeq_relaxed(v, c)
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#define gic_read_lpir(c) readq_relaxed(c)
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#define gic_write_lpir(v, c) writeq_relaxed(v, c)
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#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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#define gits_read_baser(c) readq_relaxed(c)
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#define gits_write_baser(v, c) writeq_relaxed(v, c)
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#define gits_read_cbaser(c) readq_relaxed(c)
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#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
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#define gicr_read_propbaser(c) readq_relaxed(c)
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#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
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#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
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#define gicr_read_pendbaser(c) readq_relaxed(c)
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#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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