threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
105 lines
2.3 KiB
Devicetree
105 lines
2.3 KiB
Devicetree
/*
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* Copyright (c) 2020 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&pio {
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/*
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sia81xx_gpio_R: sia81xx_gpio_R {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
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slew-rate = <1>;
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bias-disable;
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};
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};
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*/
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sia81xx_gpio_L: sia81xx_gpio_L {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO131__FUNC_GPIO131>;
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slew-rate = <1>;
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bias-disable;
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};
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};
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};
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&odm {
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sia81xx_R: sia81xx@R {
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compatible = "si,sia8152";
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si,sia81xx_type = "sia8152";
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// si,sia81xx_reset = <&pio 3 0>;
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// si,sia81xx_owi = <&pio 3 0>;
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// pinctrl-names = "sia81xx_gpio";
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// pinctrl-0 = <&sia81xx_gpio_R>;
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si,sia81xx_disable_pin = <1>;
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/* the same value share a same task
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* valid value range : 0 ~ 7 */
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timer_task_hdl = <0>;
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channel_num = <0>;
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owi_mode = <1>;
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en_x_filter = <0>;
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en_dynamic_updata_vdd = <1>;
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en_dynamic_updata_pvdd = <1>;
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dynamic_updata_vdd_port = <0x2>;
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};
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sia81xx_L: sia81xx@L {
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compatible = "si,sia8109";
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si,sia81xx_type = "sia81x9";
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si,sia81xx_reset = <&pio 131 0>;
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si,sia81xx_owi = <&pio 131 0>;
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pinctrl-names = "sia81xx_gpio";
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pinctrl-0 = <&sia81xx_gpio_L>;
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si,sia81xx_disable_pin = <0>;
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/* the same value share a same task
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* valid value range : 0 ~ 7 */
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timer_task_hdl = <0>;
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channel_num = <1>;
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owi_mode = <1>;
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en_x_filter = <0>;
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en_dynamic_updata_vdd = <1>;
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en_dynamic_updata_pvdd = <0>;
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dynamic_updata_vdd_port = <0x2>;
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};
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};
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&sound {
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si,sia81xx-max-num = <2>;
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si,sia81xx-aux-devs = <&sia81xx_R>, <&sia81xx_L>;
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si,sia81xx-aux-devs-prefix = "SpkrRight", "SpkrLeft";
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};
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&i2c6 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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mediatek,use-open-drain;
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sia81xx_i2c_R: sia81xx_i2c@R {
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compatible = "si,sia8152-i2c";
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reg = <0x58>;
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si,sia81xx-dev = <&sia81xx_R>;
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};
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sia81xx_i2c_L: sia81xx_i2c@L {
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compatible = "si,sia8109-i2c";
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reg = <0x2a>;
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si,sia81xx-dev = <&sia81xx_L>;
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};
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};
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