threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/*
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* arch/arm/plat-orion/include/plat/pcie.h
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*
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* Marvell Orion SoC PCIe handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __PLAT_PCIE_H
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#define __PLAT_PCIE_H
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struct pci_bus;
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u32 orion_pcie_dev_id(void __iomem *base);
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u32 orion_pcie_rev(void __iomem *base);
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int orion_pcie_link_up(void __iomem *base);
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int orion_pcie_x4_mode(void __iomem *base);
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int orion_pcie_get_local_bus_nr(void __iomem *base);
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void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
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void orion_pcie_reset(void __iomem *base);
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void orion_pcie_setup(void __iomem *base);
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int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val);
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#endif
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