threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/*
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* arch/arm/mach-tegra/reset.h
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*
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* CPU reset dispatcher.
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*
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* Copyright (c) 2011, NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_RESET_H
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#define __MACH_TEGRA_RESET_H
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#define TEGRA_RESET_MASK_PRESENT 0
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#define TEGRA_RESET_MASK_LP1 1
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#define TEGRA_RESET_MASK_LP2 2
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_DATA_SIZE 6
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#ifndef __ASSEMBLY__
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#include "irammap.h"
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extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra20_cpu1_resettable_status_offset(void);
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void __tegra_cpu_reset_handler_end(void);
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra_cpu_lp2_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra20_cpu1_resettable_status \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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(u32)__tegra20_cpu1_resettable_status_offset))
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#endif
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#define tegra_cpu_reset_handler_offset \
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((u32)__tegra_cpu_reset_handler - \
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(u32)__tegra_cpu_reset_handler_start)
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#define tegra_cpu_reset_handler_size \
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(__tegra_cpu_reset_handler_end - \
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__tegra_cpu_reset_handler_start)
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void __init tegra_cpu_reset_handler_init(void);
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#endif
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#endif
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